IP Library Granted Patent US 6,882,227
Granted Patent B2
US 6,882,227 · App. 10/662,849 · Granted Apr 19, 2005

Bias circuit linearization and dynamic power control

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Quick Facts
Patent No.
US 6,882,227
App. No.
10/662,849
Granted
Apr 19, 2005
Kind
B2
Abstract

A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.

Claims (16)

1. A circuit for biasing an amplifier transistor comprising a control terminal, a current-sink terminal, and a current-source terminal, the circuit comprising:

a bias transistor including a control terminal, current-sink terminal, and a current-source terminal;

a first DC input port connected to the current sink terminal of the bias transistor;

a first resonator element operatively coupled to the current-sink terminal of the bias transistor and ground;

a second DC input port connected to the control terminal of the bias transistor;

a diode element operatively coupled to the control terminal of the bias transistor and ground;

a second resonator element operatively coupled to the control terminal of the bias transistor and ground; and

a resistive element operatively coupled to the current source terminal of the bias transistor and the control terminal of the amplifier transistor.

2. The circuit as set forth in claim 1 wherein the bias transistor is one of a BJT, an HBT and a FET.

3. The circuit as set forth in claim 1 wherein the amplifier transistor is one of a BJT, an HBT and a FET.

4. The circuit as set forth in claim 1 wherein the first resonator is an RLC circuit.

5. The circuit as set forth in claim 1 wherein the diode element comprises a plurality of diodes.

6. The circuit as set forth in claim 1 wherein the second resonator is an RLC circuit.

7. The circuit as set forth in claim 1 wherein the resistive element is a resistor.

8. The circuit as set forth in claim 1 wherein the resistive element is an RLC circuit.

9. The circuit as set forth in claim 8 wherein the resistive element further comprises a resistor.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2017
From: II-VI OPTOELECTRONIC DEVICES, INC.
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 042551/0708 →
CHANGE OF NAME Recorded May 1, 2017
From: ANADIGICS, INC.
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 042381/0761 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS NUMBER 6790900 AND REPLACE IT WITH 6760900 PREVIOUSLY RECORDED ON REEL 034056 FRAME 0641. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Nov 21, 2016
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 040660/0967 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 037973 FRAME: 0226. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded May 18, 2016
From: ANADIGICS, INC.
To: II-VI INCORPORATED
Reel/Frame 038744/0835 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2016
From: II-VI INCORPORATED
To: ANADIGICS, INC.
Reel/Frame 038119/0312 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 1, 2016
From: ANADIGICS, INC.
To: II-IV INCORPORATED
Reel/Frame 037973/0226 →
RELEASE OF SECURITY INTEREST Recorded Mar 1, 2016
From: SILICON VALLEY BANK
To: ANADIGICS, INC.
Reel/Frame 037973/0133 →
SECURITY AGREEMENT Recorded Oct 27, 2014
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 034056/0641 →