Data processing processor
View Patent ↗A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
1. A data processor formed on a semiconductor substrate which is connectable to a synchronous memory, comprising:
a data processing unit;
a display unit;
an image input unit;
each of the units having a priority order which indicates a memory access priority order,
a plurality of registers, and at least one of which stores an initial set value according to the priority order;
a control unit controlling arbitration to access to the synchronous memory, and allowing to one of the data processing unit, display unit and image input unit access to the synchronous memory; and
a plurality of timer units which are set at a initial set value according to the priority order,
wherein each of the data processing unit, display unit, and image input unit provides an access request to the control unit to access the synchronous memory,
wherein the control unit allows one of the units which provide access requests to access the synchronous memory according to the value of the timer unit.
2. The data processor according to claim 1 ,
wherein the timer units perform a count-down operation,
wherein one timer unit starts the count-down operation, when the control unit receives the access request corresponding to the units accessing the synchronous memory,
wherein the initial set value of a module having high priority order is smaller than the initial set value of a module having low priority order, and
wherein the control unit allows, to the unit outputting the access request, access to the synchronous memory, when the timer unit of the unit outputting the access request has the low value.
3. The data processor according to claim 2 ,
wherein the display unit has a high priority order, and the image input unit has a low priority order, and
wherein the initial set value of the high priority order is smaller than that of the low priority order.
4. The data processor according to claim 1 ,
wherein the data processing unit further comprises a memory interface unit operating to access the synchronous memory, and outputting the data signals, address signals and control signals, and inputting data signals to the synchronous memory, and
wherein the memory interface unit controls access to the synchronous memory according to arbitration of the control unit.