Method and apparatus for accurately modeling digital signal processors
View Patent ↗A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor. The behavior of the given DSP fixed-point processor is then modeled in a C++ environment using the library of classes.
1. A method of modeling a digital processor comprising:
loading operations and data representations of a target processor defined in a high level programming language, the operations and data representations being used in commands for execution by the target processor; and
in a computer system, using the defined operations and data representations, simulating the target processor executing certain commands to provide a model of the target processor data representations and operations to decrease development time of a real-time implementation of the certain commands on the target processor, the simulating including generating model data indicative of results of the target processor having executed the certain commands, the generated model data providing a bit level representation of the target processor results.
2. A method as claimed in claim 1 wherein the step of simulating includes providing the model generated data in human readable terms instead of machine code.
3. A method as claimed in claim 1 further comprising the step of executing working code on the target processor, such that the target processor generates working data, and
wherein the step of simulating includes generating model data corresponding to the working data generated by the target processor in a manner such that the model data is (i) bit-wise matchable to the target processor generated working data, and (ii) in human readable terms.
4. A method as claimed in claim 1 wherein the step of simulating further includes using the high level programming language, defining data types for the data representations of the target processor.
5. A method as claimed in claim 4 wherein the step of simulating further comprises the steps of:
for a given source processor, (a) determining each distinct fixed bit length data representation, and (b) grouping the determined distinct data representation to form a set;
for each target processor, repeating steps (a) and (b) such that respective sets are formed; and
forming a hierarchy of the formed sets by correlating one set to another such that a base class with depending subclasses are generated and form the hierarchy, each set being defined by one of the base class and a subclass.
6. A method as claimed in claim 4 wherein the step of defining operations is incremental such that one target processor operation at a time is defined and modeled using the high level programming language.
7. A method as claimed in claim 1 further comprising the step of generating diagnostic data corresponding to the simulating.
8. A method as claimed in claim 7 wherein the step of generating diagnostic data includes indicating the number of times different operations of the target processor are encountered during the simulating.
9. A method as claimed in claim 1 wherein the step of simulating is incremental, such that a first set of certain data representations and operations of the target processor is simulated using the high level programming language to form an intermediate model of the target processor, and subsequent to the formation of the intermediate model, at least a second set of data representations and operations of the target processor is simulated using the high level programming language to increment the intermediate model toward a final desired model of the target processor.
10. A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions that, when executed by a digital processor, cause the processor to perform:
loading operations and data representations of a target processor defined in a high level programming language, the operations and data representations being used in commands for execution by the target processor; and
in the processor, using the defined operations and data representations, simulating the target processor executing certain commands to provide a model of the target processor data representations and operations to decrease development time of a real-time implementation of the certain commands on the target processor, the simulating including generating model data indicative of results of the target processor having executed the certain commands, the generated model data providing a bit level representation of the target processor results.
11. The computer-readable medium according to claim 10 wherein the instructions causing the processor to perform simulating the target processor include instructions that cause the processor to perform providing the model generated data in human readable terms instead of machine code.
12. The computer-readable medium according to claim 10 wherein the instructions further include instructions causing the processor to perform executing working code on the target processor, such that the target processor generates working data, wherein the instructions causing the processor to perform simulating the target processor include generating model data corresponding to the working data generated by the target processor in a manner such that the model data is (i) bit-wise matchable to the target processor generated working data, and (ii) in human readable terms.
13. The computer-readable medium according to claim 10 wherein the instructions causing the processor to perform simulating the target processor further include instructions that cause the processor to perform, using the high level programming language, defining data types for the data representations of the target processor.
14. The computer-readable medium according to claim 13 wherein the instructions causing the processor to perform simulating further include instructions that cause the processor to perform:
for a given source processor, (a) determining each distinct fixed bit length data representation, and (b) grouping the determined distinct data representation to form a set; for each target processor, repeating steps (a) and (b) such that respective sets are formed; and
forming a hierarchy of the formed sets by correlating one set to another such that a base class with depending subclasses are generated and form the hierarchy, each set being defined by one of the base class and a subclass.
15. The computer-readable medium according to claim 13 wherein the instructions causing the processor to perform defining data types is incremental such that one target processor operation at a time is defined and modeled using the high level programming language.
16. The computer-readable medium according to claim 10 wherein the instructions further include instructions that cause the processor to perform generating diagnostic data corresponding to the simulating the target processor.
17. The computer-readable medium according to claim 16 wherein the instructions causing the processor to perform generating diagnostic data further include instructions that cause the processor to perform indicating the number of times different operations of the target processor are encountered during the simulating the target processor.
18. The computer-readable medium according to claim 10 wherein the instructions causing the processor to perform simulating the target processor further include instructions that cause the processor to perform (i) simulating in an incremental manner, such that a first set of certain data representations and operations of the target processor is simulated using the high level programming language to form an intermediate model of the target processor, and (ii) subsequent to the formation of the intermediate model, simulating at least a second set of data representations and operations of the target processor using the high level programming language to increment the intermediate model toward a final desired model of the target processor.
19. An apparatus for modeling a digital processor, comprising:
a source of operations and data representations of a target processor defined in a high level programming language, the operations and data representations being used in commands for execution by the target processor; and
a computer system using the defined operations and data representations, the computer system simulating the target processor executing certain commands to provide a model of the target processor data representations and operations to decrease development time of a real-time implementation of the certain commands on the target processor, the computer system generating model data indicative of results of the target processor having executed the certain commands, the generated model data providing a bit level representation of the target processor results.
20. The apparatus as claimed in claim 19 wherein the computer system provides the model generated data in human readable terms instead of machine code.
21. The apparatus as claimed in claim 19 further including a target processor in communication with the computer system, wherein the target processor executes working code such that the target processor generates working data, and wherein the computer system generates model data corresponding to the working data generated by the target processor in a manner such that the model data is (i) bit-wise matchable to the target processor generated working data, and (ii) in human readable terms.
22. The apparatus as claimed in claim 19 wherein the computer system uses the high level programming language and defines data types for the data representations of the target processor.
23. The apparatus as claimed in claim 22 wherein:
for a given source processor, the computer system (a) determines each distinct fixed bit length data representation, and (b) groups the determined distinct data representation to form a set;
for each target processor, the computer system repeats steps (a) and (b) such that respective sets are formed; and
the computer system forms a hierarchy of the formed sets by correlating one set to another such that a base class with depending subclasses are generated and form the hierarchy, each set being defined by one of the base class and a subclass.
24. The apparatus as claimed in claim 22 wherein the computer system defines operations incrementally such that one target processor operation at a time is defined and modeled using the high level programming language.
25. The apparatus as claimed in claim 19 wherein the computer system generates diagnostic data corresponding to simulating of the target processor.
26. The apparatus as claimed in claim 25 wherein the diagnostic data includes indications of a number of times different operations of the target processor are encountered during the simulation of the target processor by the computer system.
27. The apparatus as claimed in claim 19 wherein the computer system simulates the target processor incrementally, such that the computer system simulates a first set of certain data representations and operations of the target processor using the high level programming language to form an intermediate model of the target processor, and subsequent to the formation of the intermediate model, the computer system simulates at least a second set of data representations and operations of the target processor using the high level programming language to increment the intermediate model toward a final desired model of the target processor.