Granted Patent B1

US 7,451,270 · App. 10/675,841 · Granted Nov 11, 2008

Abstract

Claims (51)

1. A control system, comprising:

a storage device to store data signals and a mode designator, the mode designator to select a first or a second mode of operation, wherein the storage device includes a memory having multiple addressable storage locations, each for storing a different respective set of data signals and a respective mode designator to control how the data signals are to be utilized after the data signals stored at the addressable storage location are read from the memory;

a circuit coupled to the storage device to receive as control signals predetermined ones of the data signals along with the respective mode designators to control whether the circuit operates in a first mode or a second mode, the control signals to control operation of the circuit when the circuit is operating in the first mode; and

Error Correction Code (ECC) logic coupled to the storage device to interpret the predetermined ones of the data signals as ECC check bits to detect errors in the data signals when the circuit is operating in the second mode.

2. The system of claim 1 , wherein the circuit includes branch logic to utilize the predetermined ones of the data signals stored at an addressable storage location to generate a next address for addressing the memory if the mode designator stored at the addressable storage location indicates the circuit will operate in the first mode.

3. The system of claim 1 , wherein the circuit includes logic to provide one or more functions of an instruction processor.

4. The system of claim 1 and further including a programmable storage device coupled to the circuit to select the predetermined ones of the data signals.

5. The system of claim 1 , and further including at least one parity circuit coupled to the storage device to determine whether a parity error occurred on any of a predetermined set of the data signals.

6. The system of claim 5 , wherein the at least one parity circuit includes a circuit to determine whether a parity error occurred on the predetermined set of the data signals when the circuit is operating in the second mode.

7. The system of claim 1 , wherein the ECC logic is coupled to ECC complement logic to correct errors in the data signals that are detected by the ECC logic when operating in the second mode.

8. The system of claim 7 , and further including logic coupled to the ECC complement logic to provide the data signals to the circuit for use as control signals after any errors detected by the ECC logic have been corrected.

9. A method of controlling a digital system, wherein the digital system includes a memory having multiple addressable storage locations, each storing a different respective set of data signals and wherein each of the addressable storage locations includes circuits to store a respective mode designator to control whether the system operates in a first mode or a second mode after the data signals stored at the addressable storage location are read from the memory, the method comprising:

a.) reading first data signals along with a mode indicator from one of the multiple addressable storage locations in the storage device;

b.) interpreting the first data signals as control signals to control one or more functions of the digital system if operating in a first mode of operation as determined by a state of the mode indicator; and

c.) interpreting the first data signals as Error Correction Code (ECC) signals if operating in a second mode of operation as determined by the state of the mode indicator.

10. The method of claim 9 , and further including:

reading second data signals from the storage device; and

using the ECC signals to detect errors in the second data signals if operating in the second mode of operation.

11. The method of claim 10 , wherein the storage device is a memory, and wherein the first and second data signals are stored at a same addressable location within the memory.

12. The method of claim 11 , wherein multiple memory addresses each stores different respective first and second data signals.

13. The method of claim 12 , and further including using the first data signals to generate a next address for addressing the memory when operating in the first mode of operation.

14. The method of claim 12 , and further including:

reading one of the multiple memory addresses; and

interpreting at least one of the second data signals as the mode indicator to indicate whether operation is occurring in the first or the second mode of operation.

15. The method of claim 14 , and Including repeating the steps of claim 17 for each of multiple memory addresses.

16. The method of claim 10 , and further including, correcting an error if the error is detected in predetermined ones of the second data signals.

17. The method of claim 16 , and further including programmably selecting the predetermined ones of the second data signals.

18. The method of claim 9 , and further including programmably selecting the first data signals.

19. The method of claim 10 , and further including interpreting one or more of the second data signals as control signals to control an arithmetic logic unit of an instruction processor.

20. The method of claim 10 , an further including using parity bits to detect a parity error occurring within the first or the second data signals.

21. The method of claim 20 , and further including:

reporting any error detected using the ECC signals; and

reporting any error detected using the parity bits.

22. The method of claim 21 , and further including:

servicing any error detected by the ECC signals at a time that is optimal for the digital system; and

servicing any error detected using the parity bits substantially immediately.

23. A control system having a first and second mode of operation, comprising:

storage means for storing data signals and mode designators, wherein the storage means includes multiple addressable means, each for storing a different respective set of data signals and wherein each of the addressable means includes mode means for storing a respective mode designator, a state of the mode designator for selecting between operation in the first mode or the second mode after the data signals stored at the addressable means are read from the storage means;

control means for receiving the data signals with the mode designator, and for utilizing first ones of the data signals to affect operations of the control system when operating in the first mode; and

error means for interpreting the first ones of the data signals as check bits for detecting errors occurring in second ones of the data signals when the control system is operating in the second mode.

24. The system of claim 23 , wherein the storage means includes means for storing the mode designator to control whether the control system is operating in the first or the second mode.

25. The system of claim 23 , wherein the control means includes branch means for utilizing the first ones of the data signals to generate an address for the storage means.

26. The system of claim 23 , wherein the storage means is a memory including predetermined addressable locations, each storing a different respective set of the first and second ones of the data signals.

27. The system of claim 26 , wherein each of the predetermined addressable locations within the memory includes means for storing a mode designator for controlling whether the control system operates in the first or the second mode when the first and the second ones of the data signals stored at the addressable location are read from the memory.

28. The system of claim 27 , wherein the error means includes means for correcting an error detected on predetermined ones of the second ones of the data signals when the control system is operating in the second mode.

29. The system of claim 28 , and further including means for providing corrected ones of the second ones of the data signals to the control means for use in affecting the operations of the control system.

30. The system of claim 28 , and further including parity detection means for detecting parity errors within the first or the second ones of the data signals.

31. The system of claim 30 , wherein the parity detection means includes means for detecting uncorrected parity errors remaining within the second ones of the data signals.

32. The system of claim 30 , and further including maintenance means for performing error recovery actions within a first time period for errors detected by the parity detection means and, for errors detected by the error means, performing error recovery actions any time the control system is appropriately configured.

33. The system of claim 23 , and further including means for programmably selecting the first ones of the data signals.

34. The system of claim 28 , and further including means for programmably selecting the predetermined ones of the second ones of the data signals.

Assignments (13)