Liquid crystal displays including organic passivation layer contacting a portion of the semiconductor layer between source and drain regions
View Patent ↗A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In this case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.
1. A thin film transistor substrate for a liquid crystal display comprising:
a transparent insulating substrate;
a gate line disposed on the first insulating substrate;
a storage capacitor electrode disposed on the insulating substrate;
a gate insulating layer that covers the gate line and the storage capacitor electrode;
a semiconductor layer disposed on the gate insulating layer;
a data line that crosses the gate line and is disposed on the gate insulating layer;
a metal pattern that is disposed over the storage capacitor electrode, and is disposed on the same layer with the data line;
a passivation layer that comprises an organic insulating material and is disposed on the semiconductor layer and the data line, and has a contact hole that exposes the metal pattern; and
a pixel electrode connected to the metal pattern through the contact hole; wherein the passivation layer contacts a portion of the semiconductor layer between source and drain regions thereof.
2. The thin film transistor substrate of claim 1 , wherein the dielectric constant of the passivation layer is in a range of about 2.4-4.7.
3. The thin film transistor substrate of claim 1 , wherein the passivation layer has a flat surface.
4. The thin film transistor substrate of claim 1 , wherein the pixel electrode overlaps at least a portion of the data line.