IP Library Granted Patent US 6,939,207
Granted Patent B2
US 6,939,207 · App. 10/678,727 · Granted Sep 6, 2005

Method and apparatus for controlling CMP pad surface finish

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Quick Facts
Patent No.
US 6,939,207
App. No.
10/678,727
Granted
Sep 6, 2005
Kind
B2
Abstract

A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

Claims (35)

1. A method for improving step height performance in a CMP process for polishing semiconductor wafers, the method comprising:

mounting a polishing pad onto a semiconductor wafer polisher and moving the polishing surface;

reducing a roughness of the polishing surface;

scanning a length of a polishing surface of the polishing pad and obtaining polishing surface scan data;

determining a polishing surface flatness from the polishing surface scan data; and

discontinuing roughness reduction of the polishing surface when the determined polishing surface flatness reaches a desired polishing surface flatness.

2. The method of claim 1 , wherein reducing the roughness of the polishing surface comprises pressing a pad pre-conditioning member against a portion of the polishing pad surface configured to receive a semiconductor wafer.

3. The method of claim 1 , wherein reducing the roughness of the polishing surface comprises pressing a pad pre-conditioning member against a portion of the polishing pad surface configured to receive a semiconductor wafer while the polishing surface is moving.

4. The method of claim 2 , wherein the pad pre-conditioning member comprises a semiconductor wafer.

5. The method of claim 4 , wherein the semiconductor wafer comprises a TEOS oxide layer.

6. The method of claim 2 , wherein the pad pre-conditioning member comprises a plurality of discrete elements.

7. The method of claim 1 , wherein the polishing surface scan data comprises data containing peak-to-valley distance measurements for points along the length of polishing surface scanned, and wherein determining the polishing surface flatness from the polishing surface scan data comprises averaging peak-to-valley distance measurements and obtaining a roughness average.

8. The method of claim 7 , wherein the desired polishing surface flatness comprises a roughness average of less than a roughness average of a polishing surface of an unused polishing pad.

9. The method of claim 2 , wherein the pad pre-conditioning member comprises a non-abrasive material.

10. The method of claim 1 , wherein reducing the roughness of the polishing surface comprises:

(a) applying pressure against the polishing surface with a non-abrasive pad pre-conditioning member;

(b) moving the polishing surface under the preconditioning member;

(c) applying a slurry to the polishing surface; and

(d) maintaining steps (a)-(c) while keeping the polishing surface free of any abrasive pad conditioning device.

11. A method for pre-conditioning a polishing pad to improve planarity of semiconductor wafers subsequently processed in a CMP process using the polishing pad, the method comprising:

moving a polishing pad free of fixed abrasive particles;

flattening a polishing surface of the polishing pad with a pre-conditioning member; and

applying a fluid to the polishing pad while flattening the polishing surface.

12. The method of claim 11 , wherein the pre-conditioning member comprises a semiconductor material.

13. The method of claim 11 , wherein the pre-conditioning member comprises sandpaper.

14. The method of claim 11 , further comprising measuring a flatness criteria of the polishing surface after flattening the polishing pad, polishing a semiconductor wafer with the polishing pad, measuring a planarity of the semiconductor wafer after polishing the semiconductor wafer with the polishing pad, and flattening at least one additional polishing pad until the measured flatness criteria is achieved if the planarity of the semiconductor wafer is a desired planarity.

15. A method for pre-conditioning a polishing pad to improve planarity of semiconductor wafers subsequently processed in a CMP process using the polishing pad, the method comprising:

moving a polishing pad free of fixed abrasive particles;

flattening a polishing surface of the polishing pad with a pre-conditioning member; and

measuring a flatness criteria of the polishing pad.

16. The method of claim 15 , wherein measuring the flatness criteria comprises measuring a temperature of the polishing surface while flattening the polishing surface.

17. A method for pre-conditioning a new polishing pad to improve planarity of semiconductor wafers subsequently processed in a CMP process using the polishing pad, the method comprising:

applying a pre-conditioning member to the new polishing pad, wherein the new polishing pad is free of fixed abrasive particles;

flattening a polishing surface of the new polishing pad with the pre-conditioning member to reduce a roughness of the polishing surface;

measuring a surface flatness of the polishing surface; and discontinuing the flattening of the polishing surface when a desired surface flatness is attained.