Process for passivating polysilicon and process for fabricating polysilicon thin film transistor
View Patent ↗A process for passivating polysilicon and a process for fabricating a polysilicon thin film transistor. A polysilicon layer is formed. Next, high-pressure annealing is performed using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or mixtures thereof to passivate the polysilicon layer.
1. A process for passivating polysilicon, comprising the following steps:
forming a polysilicon layer; and
annealing using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, or mixtures thereof to passivate the polysilicon layer in a single step, wherein the step of forming the polysilicon layer comprises forming an amorphous silicon layer, and crystallizing the amorphous silicon layer to convert the amorphous silicon layer into the polysilicon layer, and the annealing step is conducted at a pressure of 1 atm to 20 atm.
2. The process as claimed in claim 1 , wherein the annealing step is conducted at a pressure of 2 atm to 20 atm.
3. The process as claimed in claim 1 , wherein the annealing step is conducted at a temperature of 300° C. to 600° C.
4. The process as claimed in claim 1 , wherein the annealing step uses a fluorine-containing gas.
5. The process as claimed in claim 4 , wherein the fluorine-containing gas is NF3, F2, or a mixture thereof.
6. A process for fabricating a polysilicon thin film transistor, comprising the following steps:
forming a polysilicon layer on a substrate; and
annealing using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, or mixtures thereof to passivate the polysilicon layer in a single step , wherein the step of forming the polysilicon layer comprises forming an amorphous silicon layer, and crystallizing the amorphous silicon layer to convert the amorphous silicon layer into the polysilicon layer, and the annealing step is conducted at a pressure of 1 atm to 20 atm.
7. The process as claimed in claim 6 , wherein the annealing step is conducted at a pressure of 2 atm to 20 atm.
8. The process as claimed in claim 6 , wherein the annealing step is conducted at a temperature of 300° C. to 600° C.
9. The process as claimed in claim 6 , wherein after the polysilicon layer is formed, the passivation step is directly performed without forming other films.
10. The process as claimed in claim 6 , further comprising, after the polysilicon layer is formed and before the passivation step, the following step:
forming a gate dielectric layer on the polysilicon layer.
11. The process as claimed in claim 10 , further comprising, after the gate dielectric layer is formed and before the passivation step, the following step:
forming a gate on the gate dielectric layer.
12. The process as claimed in claim 10 , after the gate dielectric layer is formed and before the passivation step, further comprising the following step:
doping the polysilicon layer to form a source/drain region.
13. The process as claimed in claim 12 , wherein the annealing step simultaneously passivates the polysilicon layer and activates the source/drain region.
14. The process as claimed in claim 6 , wherein the annealing step uses a fluorine-containing gas.
15. The process as claimed in claim 14 , wherein the fluorine-containing gas is NF3, F2, or a mixture thereof.
16. A process for fabricating a polysilicon thin film transistor, comprising;
forming a polysilicon layer on a substrate;
forming a gate dielectric layer on the polysilicon layer;
forming a gate on the gate dielectric layer;
doping the polysilicon layer to form source/drain regions by using the gate as a mask;
forming source/drain electrodes for the source/drain regions respectfully; and
annealing using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, or mixtures thereof to passivate the polysilicon layer in a single step.