Semiconductor integrated circuit device operating with low power consumption
View Patent ↗Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.
1. A semiconductor device comprising:
a normal array having a plurality of normal memory cells;
a redundant array having spare memory cells for repairing a defective normal memory cell having a defect in said normal array;
a normal access circuit for accessing a selected normal memory cell in said normal array, said normal access circuit including, as a component thereof, an insulated gate field effect transistor;
a spare access circuit for accessing the spare memory cell in said redundant array, said spare access circuit including, as a component thereof, an insulated gate field effect transistor; and
a power supply control circuit for setting a gate tunnel current of the insulated gate field effect transistor of an inactive circuit out of said spare access circuit and said normal access circuit to be smaller than the gate tunnel current of the transistor in an active circuit out of the spare and normal access circuits.
2. The semiconductor device according to claim 1 , wherein
each of said spare and normal access circuits includes a plurality of sub-access circuits to be activated selectively; and
said power supply control circuit sets the unselected sub-access circuit in said spare and normal access circuits to the state causing a gate tunnel current smaller than the gate tunnel current of the transistor in the selected sub-access circuit.
3. The semiconductor device according to claim 1 , further comprising:
a determining circuit for determining which is to be activated between the normal and spare access circuits in accordance with an address signal, and activating one of said normal and spare access circuits in accordance with a result of determination, said determining circuit starting the determining operation before activation of an operation mode instructing signal instructing a memory cell selecting operation.
4. The semiconductor device according to claim 1 , further comprising:
a determining circuit for determining which is to be activated between the normal and spare access circuits in accordance with an address signal, and activating one of said normal and spare access circuits in accordance with a result of determination, said determining circuit executing the determining operation asynchronously to an operation mode instructing signal instructing a memory cell selecting operation.