Increasing memory locality of filesystem synchronization operations
View Patent ↗A cache class in a software-administered cache of a multiprocessor is assigned cache space that is localized to a single region of a memory and is contiguous. Synchronization and LRU operations can step sequentially through the given region, removing the need for SLB searches or the penalty for a miss, while other threads remain random access. The threads that manage each virtual memory area can then be attached to specific processors, maintaining physical locality as well.
1. A multiprocessor system comprising:
a plurality of processors;
a plurality of memories associated with and residing on a chip with at least some of said plurality of processors; and
a software-administered cache located in said plurality of memories, said cache being separated into a plurality of cache classes, cache memory associated with each of said cache classes being located within a single region of a plurality of regions within one of said memories, and each of said plurality of cache classes being allocated a plurality of pages in contiguous memory,
wherein a first thread, performing at least one administrative function within said cache, is connected to operate sequentially through the single region.
2. The multiprocessor system of claim 1 , wherein said administrative function is a least-recently-used algorithm for one of said plurality of cache classes.
3. The multiprocessor system of claim 1 , wherein said administrative function is a synchronizing algorithm for one of said plurality of cache classes.
4. The multiprocessor system of claim 1 , wherein a second thread reads said memory randomly.
5. The multiprocessor system of claim 1 , wherein said software-administered cache is administered by an AIX operating system and said region is a segment.
6. The multiprocessor system of claim 1 , wherein said first thread is always spawned by a processor located on a same chip as a cache memory associated with a first cache class of said plurality of cache classes on which said thread operates.
7. A method of managing a software-administered cache memory in a multiprocessor, comprising the steps of:
associating a plurality of metadata objects with a first cache class of a plurality of cache classes, wherein cache space for said plurality of metadata objects in said first cache class is administered as a single entity;
allocating a plurality of pages of software-administered cache memory to said first cache class, said plurality of pages being within a single region of a memory having a plurality of regions, and being in contiguous memory; and
spawning a thread to sequentially access said plurality of pages of cache memory through the single region for an administrative function.
8. The method of claim 7 , wherein said administrative function is a least-recently-used algorithm for said first cache class.
9. The method of claim 7 , wherein said administrative function is a synchronizing algorithm for said first cache class.
10. The method of claim 7 , wherein other threads acting on said cache class read randomly.
11. The method of claim 7 , wherein said software administered cache is a UNIX operating system cache.
12. The method of claim 7 , wherein said region is a segment in a segmented architecture.
13. The method of claim 7 , wherein a memory containing said region is on the same chip as a processor spawning said thread.
14. A computer program product, comprising:
a computer readable medium having computer readable program code for managing a software-administered cache memory in a multiprocessor, the computer program product comprising;
computer readable program code configured for associating a plurality of metadata objects with a first cache class of a plurality of cache classes, wherein cache space for said plurality of metadata objects in said first cache class is administered as a single entity;
computer readable program code configured for allocating a plurality of pages of software-administered cache memory to said first cache class, said plurality of pages being within a single region of a memory having a plurality of regions, and being in contiguous memory; and
computer readable program code configured for spawning a thread to sequentially access said plurality of pages of cache memory through the single region for an administrative function.