Monolithic integrated circuit with a printhead interface

1. A monolithic integrated circuit which comprises

programmable processing circuitry;

a printhead interface that is connected to the processing circuitry and is configured to receive data from the processing circuitry and to generate control signals to be received by a pagewidth printhead of a printing mechanism, the printhead interface being directly connectable to the pagewidth printhead;

a first image sensor interface that is connected to the processing circuitry and is configured to receive image manipulation signals from a first image sensor and to pass image manipulation data representing the image manipulation signals to the programmable processing circuitry;

a second image sensor interface that is connected to the processing circuitry and is configured to receive visual image signals from a second image sensor and to pass visual image data representing the visual image signals to the programmable processing circuitry; and

a force sensor interface that is connected to the programmable processing circuitry, wherein when a force is applied to a print medium which the pagewidth printhead uses for printing the manipulated image, the force sensor interface receives a force sensor signal indicating a force has been applied to the print meduim, wherein in response to the force sensor signal the programmable processing circuitry is configured to transfer an actuation signal to a guillotine actuator so that the print medium is severed by a guillotine;

wherein the programmable processing circuitry is configured to manipulate the visual image data using the image manipulation data to generate a manipulated visual image, wherein the manipulated visual image data representing the manipulated visual image is received by the printhead interface for printing the manipulated image.

2. An integrated circuit as claimed in claim 1 , in which the programmable processing circuitry includes at least four substantially identical processing units that are configured for parallel operation and switching circuitry connecting the processing units operatively to each other.

3. An integrated circuit as claimed in claim 1 , which includes an output FIFO buffer, the processing circuitry being configured to communicate with the printhead interface via the output FIFO buffer.

4. An integrated circuit as claimed in claim 1 , which includes an input FIFO buffer, the processing circuitry being configured to communicate with the image sensor interface via the input FIFO buffer.

5. An integrated circuit as claimed in claim 1 , in which the printhead interface is configured to generate control signals suitable for a pagewidth printhead having at least one printhead chip.

6. A digital camera device which includes an integrated circuit as claimed in claim 1 .

7. The integrated circuit according to claim 1 , wherein the image manipulation data is encoded, wherein the programmable processing circuitry is configured to decode the encoded image manipulation data.