Method for fabricating a semiconductor apparatus including a sealing member with reduced thermal stress
View Patent ↗A semiconductor apparatus having a semiconductor substrate including an integrated circuit and an insulative base member formed on a main surface thereof. A conductive layer is formed on the main surface of the semiconductor substrate as coupled to the integrated circuit and includes an external portion that extends onto top surface of the base member. A sealing member is formed on the main surface of the semiconductor substrate, the conductive layer and side surfaces of the base member, whereby the extended portion of the conductive layer is exposed from the sealing member.
1. A method for fabricating a semiconductor apparatus comprising:
forming a semiconductor integrated circuit on a first surface of a semiconductor substrate;
forming a base member of insulating material on the first surface of the semiconductor substrate;
forming a conductive layer directly on the first surface of the semiconductor substrate, the conductive layer being connected to the semiconductor integrated circuit and having an extended portion that extends onto a top surface of the base member;
placing the first surface of the semiconductor substrate having the semiconductor integrated circuit, the base member and the conductive layer thereon as facing a connection substrate;
connecting the extended portion of the conductive layer to the connection substrate; and
supplying a sealing member in a space between the semiconductor substrate and the connection substrate, after said connecting,
the base member and the sealing member having a same thermal expansion coefficient,
the conductive layer is formed so that the extended portion extends onto an entirety of the top surface of the base member.
2. A method according to claim 1 , wherein the base member and the sealing member are a polymide resin.