Bidirectional turbo ISI canceller-based DSSS receiver for high-speed wireless LAN
A bidirectional turbo ISI canceller cancels precursor-ISI as well as postcursor-ISI in a received signal without incorporating a multiplicative feedforward equalization filter. This is accomplished by taking a three-step receiver design approach. In the first step, an optimal single-symbol RAKE receiver is designed to comprise a CMF, a codeword correlator bank, and an energy bias (EB) canceller under the assumption that no ISI is generated by preceding or trailing symbols. In a second step, a DFE is included for suppressing postcursor-ISI caused by a preceding symbol. Finally, a precursor ISI canceler is used to remove the remaining ISI caused by a trailing symbol. All three components may be integrated into a BTIC-based receiver applying turbo-iteration processing.
1. A method for reducing signal distortion in a receiver, comprising:
deriving a sequence of chips from a received signal, wherein deriving the chip sequence includes convolving the received signal with coefficients of a filter;
canceling postcursor-inter-symbol interface (ISI) from the chip sequence to determine a current code complementary keying (CCK) codeword;
computing a chip-time reversed estimate of the current CCK codeword; and
canceling precursor-ISI from a previous CCK codeword based on the chip-time reversed estimate of the current CCK codeword.
2. The method of claim 1 , wherein deriving the chip sequence includes:
convolving the received signal with coefficients of a channel matched filter.
3. The method of claim 1 , further comprising:
generating terms for canceling the postcursor ISI from a chip sequence detected in a preceding symbol.
4. The method of claim 1 , wherein canceling postcursor-ISI includes:
generating postcursor-ISI cancellation terms from a previously detected CCK chip sequence used to form a previous CCK codeword;
subtracting the postcursor-ISI cancellation terms from the chip sequence to produce a chip metric; and
determining said current CCK codeword using said chip metric.
5. The method of claim 1 , wherein canceling postcursor-ISI includes:
setting decision feedback equalizer (DFE) coefficients based on a previously detected CCK chip sequence;
generating postcursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock;
subtracting the postcursor-ISI terms from the chip sequence to produce a chip metric.
6. The method of claim 4 , wherein the current CCK codeword is generated by inputting said chip metric into a CCK correlator.
7. The method of claim 1 , wherein canceling the precursor-ISI includes:
computing conjugates of chip values of a future symbol;
setting decision feedback equalizer (DFE) coefficients based on the conjugates;
generating precursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock; and
subtracting the precursor-ISI terms from chip metrics corresponding to the previous CCK codeword.
8. The method of claim 1 , wherein the received signal is one generated in a direct-sequence spread-spectrum (DSSS/CCK) wireless communications system.
9. The method of claim 1 , further comprising:
equalizing signal energy in a codeword correlator bank used to generate the current and previous CCK codewords.
10. The method of claim 1 , further comprising:
(a) obtaining chips of the previous CCK codeword generated after cancellation of the precursor-ISI; and
(b) performing postcursor-ISI and precursor-ISI based on the previous CCK codeword chips obtained in (a).
11. The method of claim 10 , further comprising:
repeating steps (a) and (b) a predetermined number of times.
12. A system for reducing signal distortion in a receiver, comprising:
channel matched filter which generates a sequence of chips from a received signal;
a decision feedback equalizer (DFE) which cancels postcursor- inter-symbol interferance ISI from the chip sequence to produce a chip metric; and
a code complementary keying (CCK) correlation-decision block which generates a current CCK codeword based on said chip metric, wherein the DFE cancels precursor-ISI from a previous CCK codeword based on a chip-time reversed estimate of the current CCK codeword.
13. The method of claim 12 , wherein the DFE cancels postcursor-ISI by generating postcursor-ISI correction terms from a previously detected CCK chip sequence used to form the previous CCK codeword and subtracting the postcursor-ISI correction terms from the chip sequence to produce said chip metric.
14. The system of claim 12 , wherein the DFE cancels postcursor-ISI by setting DFE coefficients based on a previously detected CCK chip sequence, generating postcursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock, and subtracting the postcursor-ISI terms from the chip sequence to produce said chip metric to produce said chip.
15. The system of claim 12 , wherein the DFE cancels the precursor-ISI by computing conjugates of chip values of a future symbol, setting DFE coefficients based on the conjugates, generating precursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock, and subtracting the precursor-ISI terms from chip metrics corresponding to the previous CCK codeword.
16. The system of claim 12 , wherein the receiver is a DSSS/CCK wireless communications receiver.
17. The system of claim 12 , further comprising:
an energy bias canceler which equalizes signal energy in the codeword correlator bank.
18. A bidirectional turbo inter-symbol interface (ISI) canceler (BTIC), comprising:
a single-symbol detector which generates a sequence of chips from a received signal;
a postcursor-ISI canceler to generate postcursor-ISI cancellation terms from a previously detected chip sequence used to form a previous code complementary keying (CCK) codeword and to cancel postcursor-ISI from the chip sequence to produce a chip metric; and
a precursor-ISI canceler to generate precursor-ISI cancellation terms based on a chip-time reversed estimate of a current CCK codeword generated from said chip metric to cancel precursor-ISI from the previous CCK codeword.
19. The bidirectional turbo ISI canceler of claim 18 , wherein the single-symbol detector includes a RAKE receiver.
20. The bidirectional turbo ISI canceler of claim 18 , comprising:
a channel matched filter which generates the chip sequence from the received signal; and
a codeword correlator bank which generates the current CCK codeword from said representation of said postcursor-ISI.
21. The bidirectional turbo ISI canceler of claim 20 , wherein the single-symbol detector further includes an energy bias canceler to equalize signal energy in the codeword correlator bank.
22. A method for reducing distortion in a receiver, comprising:
computing a set of decision feedback equalizer (DFE) coefficients;
canceling postcursor-inter-symbol interference (ISI) caused by a preceding symbol using the set of DFE coefficients; and
canceling precursor-ISI caused by a trailing symbol using the same set of DEE coefficients, wherein said canceling postcursor-ISI and the canceling precursor-ISI are respectively performed in first and second feedback canceler units based on the set of DEE coefficients, wherein canceling the precursor-ISI because of the trailing symbol comprises:
computing conjugates of chip values of a future symbol;
setting the DFE coefficients based on the DFE coefficients; and
subtracting the precursor-ISI terms from chio metrics to reduce the precursor-ISI.
23. A receiver, comprising:
a first feedback canceler to cancel postcursor-inter-symbol interference (ISI) caused by a preceding symbol;
a second canceler which cancels precursor-ISI caused by a trailing symbol, wherein the first and second cancellers use a same set of decision feedback equalizer (DFE) coefficients to cancel the postcursor-ISI and precursor-ISI, wherein the first and second feedback cancellers are included in at least one DFE, the decond feedback canceller to use the set of DFE coefficients being time-reversed to cancel the precursor-ISI.