Thin film transistor array panel used for a liquid crystal display and a manufacturing method thereof
View Patent ↗A gate insulating layer, an amorphous silicon layer, an n + amorphous silicon layer and a metal layer are deposited in sequence after a gate line, a gate electrode and a gate pad are formed on a substrate, using a first mask. The metal layer is etched to form a data line, a source electrode, a drain electrode and a data pad through a photolithography process, using a second mask, and the n + amorphous silicon layer is etched, using the patterned data line, the source electrode, the drain electrode and the data pad as the mask. A light shielding film and a passivation film, or a passivation film also having a function of the light shielding film are deposited, and is etched through the photolithography process, using a third mask which leaves a portion covering the gate line, the gate electrode, the gate pad and the data line, the source electrode, and the drain electrode. The amorphous silicon layer and the gate insulating layer are etched, using the patterned light shielding film and passivation film, or the patterned passivation film also having the function of the light shielding film as the mask. Here, the gate pad, the data pad and a part of the drain electrode are exposed. A pixel electrode connected to the drain electrode, is formed and indium tin oxide (ITO) pads covering the exposed gate pad and the exposed data pad, is formed by depositing an ITO film and etching thorough the photolithography, using a fourth mask. As a result, a thin film transistor array panel used for a liquid crystal display is fabricated by only four masks.
1. A method for manufacturing a thin film transistor array panel, comprising steps of:
forming a gate line and a gate electrode on a substrate by using a first mask;
forming an insulation layer on the gate line and on the gate electrode;
forming a semiconductor layer on the insulating layer;
forming a data line, a source electrode and a drain electrode on the substrate by using a second mask;
forming a passivation film on the semiconductor layer, the data line, the source electrode and the drain electrode by using a third mask, the passivation film exposing a portion of the drain electrode and a portion of the semiconductor layer;
removing the exposed portion of the semiconductor layer; and
forming a pixel electrode connected to the exposed portion of the drain electrode by using a fourth mask.
2. The method of claim 1 , wherein the passivation film is formed of an opaque material.
3. The method of claim 1 , wherein the passivation film overlaps portions of the gate line and the gate electrode.
4. The method of claim 3 , wherein the step of removing the exposed portion of the semiconductor layer exposes a portion of the insulating layer, and
the method further comprising a step of removing the exposed portion of the insulating layer.
5. The method of claim 4 , further comprising a step of forming a connection portion on the insulating layer, the connectinn portion overlapping a part of the gate line.
6. The method of claim 5 , wherein the passivation film exposes a part of the connection portion, and the connection portion is connected to the pixel electrode.
7. A method for manufacturing a thin film transistor array panel, comprising steps of:
depositing a first conductive layer on a substrate;
patterning the first conductive layer by using a first mask to form a gate line and a gate electrode;
depositing an insulating layer on the gate line and on the gate electrode;
depositing a semiconductor layer on the insulating layer;
depositing a second conductive layer on the insulating layer;
patterning the second conductive layer by using a second mask to form a data line, a source electrode, and a drain electrode;
depositing a passivation layer on the semiconductor layer, the drain electrode, the source electrode and the data line;
patterning the passivation layer by using a third mask to expose a portion of the semiconductor layer, a portion of the gate line, a portion of the data line, a portion of the insulating layer;
removing the exposed portion of the insulating layer;
depositing a third conductive layer on the passivation layer and the insulating layer and
patterning the third conductive layer to form a pixel electrode that contacts the exposed portion of the drain electrode by using a fourth mask.
8. The method of claim 7 , further comprising a step of forming transparent conductive pads that cover the exposed portion of the gate line and the data line, respectively.
9. The method of claim 7 , wherein the first conductive layer comprises an upper layer and a lower layer of different materials.
10. The method of claim 9 , wherein the lower layer comprises Al or an Al alloy, and the upper layer comprises Mo.
11. The method of claim 9 , wherein the lower layer comprises Cr, and the upper layer comprises Al or an Al alloy.
12. The method of claim 11 , further comprising a step of removing the exposed portion of the upper layer.
13. The method of claim 7 , wherein the step of depositing a semiconductor layer comprises steps of:
depositing an amorphous silicon layer on the insulating layer and
depositing a n+ amorphous silicon layer on the amorphous silicon layer.
14. The method of claim 13 , wherein the step of patterning the second conductive layer exposes a portion of the n+ amorphous silicon layer.
15. The method of claim 14 , further comprising a step of removing the exposed portion of the n+ amorphous silicon layer.
16. The method of claim 15 , wherein the step of removing the exposed portion of the n+ amorphous silicon layer exposes a portion of the amorphous silicon layer.