IP Library Granted Patent US 6,949,475
Granted Patent B2
US 6,949,475 · App. 10/694,035 · Granted Sep 27, 2005

Methods to reduce stress on a metal interconnect

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,949,475
App. No.
10/694,035
Granted
Sep 27, 2005
Kind
B2
Abstract

Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

Claims (16)

1. A method to fabricate a semiconductor device, the method comprising:

forming an uppermost metal interconnect on a semiconductor substrate;

forming an oxide layer on the substrate and the uppermost metal interconnect;

forming an aluminum layer on the oxide layer; and

forming a stress-relief layer on the aluminum layer to reduce stress on the metal interconnect.

2. A method as defined in claim 1 , wherein forming the stress-relief layer comprises:

performing a plasma treatment on a surface of the aluminum layer to form an aluminum oxide layer; and

annealing the aluminum oxide layer.

3. A method as defined in claim 2 , wherein the plasma treatment uses at least one of N 2 O gas and O 2 gas.

4. A method as defined in claim 3 , wherein the aluminum oxide layer is annealed in an atmosphere of inert gas.

5. A method as defined in claim 3 , wherein the aluminum oxide layer is annealed in an atmosphere of gas including at least one of N 2 O, O 2 , N 2 , and H 2 .

6. A method as defined in claim 2 , wherein the annealing is performed at a temperature of 200 to 400.

7. A method as defined in claim 2 , wherein the aluminum oxide layer is annealed in an atmosphere of inert gas.

8. A method as defined in claim 7 , wherein the inert gas is at least one of Ar and He.

9. A method as defined in claim 2 , wherein the aluminum oxide layer is annealed in an atmosphere of gas including at least one of N 2 O, O 2 , N 2 , and H 2 .

10. A method as defined in claim 1 , wherein the semiconductor device is at least one of a multi-interconnect adapted device and a power device.