Data communications circuit with multi-stage multiplexing
View Patent ↗In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.
1. A data demultiplexer for demultiplexing data from a communication link, the data demultiplexer comprising:
a higher frequency data demultiplexer which demultiplexes the data on the communication link to an intermediate frequency signal in response to a first timing signal;
a timing signal generator to generate a second timing signal in response to the first timing signal, wherein the second timing signal exhibits one pulse for every N pulses of the first timing signal, N being an integer value; and
a lower frequency data demultiplexer coupled to the higher frequency demultiplexer which demultiplexes the intermediate frequency signal to a demultipiexed data signal in response to the second timing signal;
wherein a maximum timing error of the second timing signal tolerable by the lower frequency demultiplexer substantially exceeds a maximum timing error of the first timing signal tolerable by the higher frequency demultiplexer.
2. A data demultiplexer as claimed in claim 1 wherein the higher frequency data demultiplexer and the lower frequency data demultiplexer are formed on a single circuit chip.
3. A data demultiplexer as claimed in claim 1 wherein the timing signal generator comprises circuitry to frequency-divide the first timing signal to generate the second timing signal.
4. A data demultiplexer as claimed in claim 3 wherein the circuitry to frequency-divide the first timing signal comprises a counter.
5. A data demultiplexer as claimed in claim 4 wherein the counter comprises a ring counter.
6. A data demultiplexer as claimed in claim 1 further comprising a multiplying delay locked loop bit clock generator to generate the first timing signal.
7. A data demultiplexer as claimed in claim 1 wherein the data on the communication link comprises a one-bit-wide bitstream.
8. A data demultiplexer as claimed in claim 7 wherein the intermediate frequency signal is two bits wide.
9. A data demultiplexer as claimed in claim 1 wherein the intermediate frequency signal comprises more than two parallel bits.
10. A data demultiplexer as claimed in claim 9 wherein the first timing signal comprises an N-phase overlapping clock.
11. A method of demultiplexing data from a communication link comprising:
demultiplexing the data from the communication link to an intermediate frequency signal in response to a first timing signal;
generating a second timing signal in response to the first timing signal, wherein the second timing signal exhibits one pulse for every N pulses of the first timing signal, N being an integer value; and
demultiplexing the intermediate frequency signal to a lower frequency signal in response to the second timing signal, wherein a maximum tolerable timing error of the second timing signal substantially exceeds a maximum tolerable timing error of the first timing signal.
12. A method of demultiplexing as claimed in claim 11 wherein demultiplexing the data from the communication link comprises demultiplexing the data within a higher frequency data demultiplexing stage and demultiplexing the intermediate frequency signal comprises demultiplexing the intermediate frequency signal within a lower frequency data demultiplexing stage, the higher frequency data demultiplexing stage and lower frequency data demultiplexing stage being formed on a single circuit chip.
13. A method of demultiplexing as claimed in claim 11 wherein generating a second timing signal in response to the first timing signal comprises frequency-dividing the first timing signal.
14. A method of demultiplexing as claimed in claim 13 wherein frequency-dividing the first timing signal in a counter comprises frequency-dividing the first timing signal in a ring counter.
15. A method of demultiplexing as claimed in claim 13 wherein frequency-dividing the first timing signal comprises frequency-dividing the first timing signal in a counter.
16. A method of demultiplexing as claimed in claim 11 further comprising generating the first timing signal within a multiplying delay locked loop bit clock generator.
17. A method of demultiplexing as claimed in claim 11 wherein the data from the communication link comprises a one-bit-wide bitstream.
18. A method of demultiplexing as claimed in claim 17 wherein the intermediate frequency signal is two bits wide.
19. A method of demultiplexing as claimed in claim 11 wherein the intermediate frequency signal comprises more than two parallel bits.
20. A method of demultiplexing as claimed in claim 19 wherein the first timing signal comprises an N-phase overlapping clock.
21. A data demultiplexer for demultiplexing data from a communication link comprising:
means for demultiplexing the data on the communication link to an intermediate frequency signal in response to a first timing signal;
means for generating a second timing signal in response to the first timing signal, wherein the second timing signal exhibits one pulse for every N pulses of the first timing signal, N being an integer value; and
means for demultiplexing the intermediate frequency signal to a lower frequency signal in response to the second timing signal, wherein a maximum tolerable timing error of the second timing signal substantially exceeds a maximum tolerable timing error of the first timing signal.