Automatic selection of data rate for optoelectronic devices
View Patent ↗Systems, devices and methods are disclosed for automatically selecting and setting an operational data rate of an optoelectronic device. In particular, an integrated circuit includes a data rate select input for the selection and setting of the operational data rate. The integrated circuit internally generates a loss of lock signal if an input data rate does not match the operational data rate. The integrated circuit then automatically sets and selects operational data rates within a predetermined range of operational data rates until the loss of lock signal is deasserted or until all of the rates within the predetermined range of operational data rates have been attempted.
1. A signal modification integrated circuit suitable for use in connection with an optoelectronic device, the signal modification integrated circuit comprising:
a receive circuit configured to operate at any one of a plurality of automatically selectable data rates and further configured to generate a loss of lock signal when a data stream associated with the receive circuit has a data rate out of range of an operational data rate at which the optoelectronic device is set, and the receive circuit being configured to set the operational data rate of the optoelectronic device to successive data rates included in the plurality of automatically selectable data rates, wherein when each data rate in the plurality of automatically selectable data rates have been set but the loss of lock signal remains asserted the receive circuit is configured to cause the data stream to be passed through the signal modification integrated circuit without modification; and
a transmit circuit configured to operate at any one of a plurality of automatically selectable data rates and further configured to generate a loss of lock signal when a data stream associated with the transmit circuit has a data rate out of range of an operational data rate at which the optoelectronic device is set, and the transmit circuit being configured to set the operational data rate of the optoelectronic device to successive data rates included in the plurality of automatically selectable data rates.
2. The signal modification integrated circuit as recited in claim 1 , wherein the signal modification integrated circuit comprises a clock data recover integrated circuit that includes an oscillator serving as a reference clock.
3. The signal modification integrated circuit as recited in claim 1 , wherein the plurality of automatically selectable data rates includes the data rates: about 4 Gb/s; and; about 2 Gb/s.
4. The signal modification integrated circuit as recited in claim 1 , wherein the receive circuit comprises one of: a receive CDR; a demultiplexer; and, a serializer.
5. The signal modification integrated circuit as recited in claim 1 , wherein the transmit circuit comprises one of: a transmit CDR; a multiplexer; and, a deserializer.
6. An optoelectronic device comprising the signal modification integrated circuit as recited in claim 1 , wherein the optoelectronic device is compatible with the Fibre Channel protocol.
7. The optoelectronic device as recited in claim 6 , wherein the optoelectronic device is compatibles with at least one of: 2 gigabits per second Fibre Channel systems; and, 4 gigabits per second Fibre Channel systems.
8. The optoelectronic device as recited in claim 6 , wherein the optoelectronic device is compatible with an input data rate of about 10 gigabits per second.
9. A transceiver module comprising the signal modification integrated circuit as recited in claim 1 , further comprising a receive optical sub-assembly configured to receive an optical data signal and converts the optical data signal to an electrical data signal; and a transmitter optical sub-assembly configured to receive an electrical data signal and convert the electrical data signal to an optical data signal.
10. The signal modification integrated circuit as recited in claim 1 , wherein the integrated circuit includes a sub-circuit that provides clock and data recovery for a plurality of data rates.
11. The signal modification integrated circuit as recited in claim 1 , wherein the integrated circuit further comprises one of: multiplexer/demultiplexer circuitry, and serializer/deserializer circuitry.