Program debug method and apparatus
View Patent ↗The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.
1. A method for debugging a first computer program, the first computer program executable on a first processor in a computer system, wherein the first processor is a specialized function processing unit (SPU), the method comprising:
activating a debugging program on a main processing unit (MPU) of the computer system, the MPU inoperable to access registers of the SPU directly;
allocating, by the debugging program, a portion of a main memory of the computer system to store received SPU register contents;
verifying, by the debugging program, that the first computer program is halted;
activating, on the SPU, a second computer program;
transferring, by the second computer program, SPU register contents to the allocated portion of the main memory;
accessing, by the debugging program, the SPU register contents from the main memory;
subsequent to accessing the SPU register contents, inspecting the SPU register contents for errors;
modifying, by the debugging program, the SPU register contents in the main memory, in response to inspecting the SPU register contents;
transferring, by the second computer program, SPU register contents from the main memory to registers of the SPU; and
restarting, by the debugging program, the SPU.
2. The method of claim 1 , further comprising transferring, by the second computer program, SPU state information to the MPU.
3. The method of claim 2 , further comprising:
allocating, by the second computer program, a portion of a local store of the SPU;
copying, by the second computer program, SPU register contents to the allocated portion of the SPU local store; and
wherein transferring, by the second computer program, SPU register contents to the allocated portion of the main memory, comprises copying the SPU register contents from the allocated portion of the SPU local store to the allocated portion of the main memory.
4. The method of claim 3 , wherein transferring, by the second computer program, SPU register contents from the main memory to registers of the SPU, further comprises:
copying the SPU register contents from the allocated portion of the main memory to the allocated portion of the SPU local store; and
loading the SPU register contents from the allocated portion of the SPU local store to the SPU registers.