Automatic generation of transaction level bus simulation instructions from bus protocol
View Patent ↗Generating transactional level bus simulation instructions from a bus protocol description is disclosed. A bus protocol description is accessed. From the bus protocol description, a finite state machine is generated. Transactional level bus simulation instructions are generated from the finite state machine. Then, the transaction level bus simulation instructions are stored in computer readable medium.
1. A method comprising:
generating transaction level bus simulation instructions by using a bus protocol comprising;
parsing the bus protocol to generate a description suitable to derive a finite state machine representative of the bus protocol; and
generating the finite state machine by using the description; and
generating a synchronous finite state machine by using the description; and
generating an optimized finite state machine by using the synchronous finite state machine; and
generating an asynchronous finite state machine by using the optimized finite state machine; and
generating hypercubes, where a given hypercube describes possible sequences of events associated with a single transition in the optimized finite sate machine; and
generating the transaction level bus simulation instructions by using the asynchronous finite state machine; and
simulating a plurality of different designs for a bus by executing the same transaction level bus simulating instructions
2. The method of claim 1 , wherein the generating the finite state machine comprises:
annotating the synchronous finite state machine with values to indicate positions of events in a pipeline.
3. A non-transitory computer-readable storage device including computer-executable instruction sorted therein, the computer-executable instructions comprising:
instructions to generate transaction level bus simulation instructions by using a bus protocol comprising;
instructions to parse the bus protocol to generate a description suitable to derive a finite state machine representative of the bus protocol; and
instructions to generate the finite state machine by using the description; and
instructions to generate a synchronous finite state machine by using the description; and
instructions to generate an optimized finite state machine by using the synchronous finite state machine; and
instructions to generate an asynchronous finite state machine by using the optimized finite state machine; and
instructions to generate hypercubes, where a given hypercube describes possible sequences of events associated with a single transition in the optimized finite sate machine; and
instructions to generate the transaction level bus simulation instructions by using the asynchronous finite state machine; and
instructions to simulate a plurality of different designs for a bus by executing the same transaction level bus simulating instructions.
4. The computer-readable storage device of claim 3 , wherein the instructions to generate the finite state machine comprise:
instructions to annotate the finite state machine with values to indicate positions of events in a pipeline.
5. A device comprising:
a memory including a plurality of instructions; and
a processor operable to execute the instructions to generate transaction level bus simulation instructions by using a bus protocol; and
the processor is further operable to execute the instructions to parse the bus protocol to generate a description suitable to derive a finite state machine repressive of the bus protocol; and
the processor is further operable to execute the instructions to generate the finite state machine by using the description; and
the processor is further operable to execute the instructions to generate a synchronous finite state machine by using the description, and wherein the processor is operable to execute the instructions to generate an optimized finite state machine by using the synchronous finite state machine; and
the processor is further operable to execute the instruction to generate a synchronous finite stat machine by using the description, and wherein the processor is operable to execute the instruction to generate an optimized finite sate machine by using the synchronous finite state machine; and
the processor is further operable to execute the instructions to generate an asynchronous finite state machine by using the optimized finite state machine; and
the processor is further operable to execute the instructions to generate hypercubes, wherein a given hypercube describes possible sequences of events associated with a single transition in the optimized finite state machine; and
wherein the processor is operable to execute the instructions to generate the transaction level bus simulation instructions by using the asynchronous finite state machine; and
wherein the processor is operable to execute the instructions to simulate a plurality of different designs for a bus by executing same transaction level bus simulation instructions.
6. The device of claim 5 , wherein the processor is operable to execute the instructions to annotate the synchronous finite state machine with values to indicate positions of events in a pipeline.