Timing verification, automated multicycle generation and verification
View Patent ↗A method for generating consistent functional and timing definitions. The method includes providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design, transforming the common source description to a functional definition, monitoring a functional simulation of the integrated circuit chip design using the functional definition, transforming the common source description to a timing definition, and performing a timing analysis of the integrated circuit chip design using the timing definition.
1. A method for generating consistent functional and timing definitions comprising:
providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design;
transforming the common source description to a functional definition;
monitoring a functional simulation of the integrated circuit chip design using the functional definition;
transforming the common source description to a timing definition, the transforming the common source description to the timing definition including
transforming the common source description to an intermediate timing definition; and,
transforming the intermediate timing definition to the timing definition; and,
performing a timing analysis of the integrated circuit chip design using the timing definition.
2. The method of claim 1 wherein:
the common source description includes information relating to a path within an integrated circuit design.
3. The method of claim 1 wherein:
the common source description includes information relating to a number of cycles a certain function within the integrated circuit design should require to complete.
4. The method of claim 1 wherein:
the common source description includes information regarding whether an expected result of a certain function within the integrated circuit design should be forced unknown or delayed.
5. The method of claim 4 wherein:
the expected result includes a true value, a false value, an unknown value and a delayed value.
6. The method of claim 5 wherein:
the delayed value corresponds to a reset signal within the common source description.
7. A system for generating consistent functional and timing definitions comprising:
a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design;
means for transforming the common source description to a functional definition;
means for monitoring a functional simulation of the integrated circuit chip design using the functional definition;
means for transforming the common source description to a timing definition, the means for transforming the common source description to the timing definition including means for transforming the common source description to an intermediate timing definition; and,
means for transforming the intermediate timing definition to the timing definition; and,
means for performing a timing analysis of the integrated circuit chip design using the timing definition.
8. The system of claim 7 wherein:
the common source description includes information relating to a path within the integrated circuit design.
9. The system of claim 7 wherein:
the common source description includes information relating to a number of cycles a certain function within the integrated circuit design should require to complete.
10. The system of claim 7 wherein:
the common source description includes information regarding whether an expected result of a certain function within the integrated circuit design should be forced unknown or delayed.
11. The system of claim 10 wherein:
the expected result includes a true value, a false value, an unknown value and a delayed value.
12. The system of claim 11 wherein:
the delayed value corresponds to a reset signal within the common source description.
13. An apparatus for generating consistent functional and timing definitions comprising:
a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design;
a transforming module, the transforming module transforming the common source description to a functional definition;
a monitoring module, the monitoring module monitoring a functional simulation of the integrated circuit chip design using the functional definition;
a timing transforming module, the timing transforming module transforming the common source description to a timing definition, the timing transforming module including
a common source to intermediate timing transforming module, the common source to intermediate timing transforming module transforming the common source description to an intermediate timing definition; and,
an intermediate to timing transform module, the intermediate to timing definition transforming module transforming the intermediate timing definition to the timing definition; and,
a timing analysis module, the timing analysis module performing a timing analysis of the integrated circuit chip design using the timing definition.
14. The apparatus of claim 13 wherein:
the common source description includes information relating to a path within the integrated circuit design.
15. The apparatus of claim 13 wherein:
the common source description includes information relating to a number of cycles a certain function within the integrated circuit design should require to complete.
16. The apparatus of claim 13 wherein:
the common source description includes information regarding whether an expected result of a certain function within the integrated circuit design should be forced unknown or delayed.
17. The apparatus of claim 16 wherein:
the expected result includes a true value, a false value, an unknown value and a delayed value.
18. The apparatus of claim 17 wherein:
the delayed value corresponds to a reset signal within the common source description.