Normalizing apparatus for adaptive beamforming in smart antenna receiving system
View Patent ↗Provided is a normalizing apparatus for adaptive beamforming by performing a normalizing process which uses a normalized least mean square (NLMS) algorithm that produces a weight vector for adaptive beamforming, in a smart antenna receiver. For the normalizing process, the normalizing apparatus includes a multiplication operation means that performs a multiplication operation, and a division operation means that performs a division operation using mathematic calculations based on binary logarithm principles, and using addition and subtraction operations.
1. A normalizing apparatus for adaptive beamforming by performing a normalizing process which uses a normalized least mean square (NLMS) algorithm that produces a weight vector for adaptive beamforming with respect to a smart antenna receiver, the apparatus comprising:
a multiplication operation means that performs a multiplication operation for the normalizing process; and
a division operation means that performs a division operation using mathematical calculation based on binary logarithmic principles and a subtraction operation, for the normalizing process.
2. The apparatus of claim 1 , further comprising a multiplexer that outputs in serial signal input from the smart antenna receiver, in synchronization with a clock signal, and inputs the signals to the multiplication operation means.
3. The apparatus of claim 2 , wherein the multiplication operation means performs the multiplication operation using mathematical calculation based on binary logarithmic principles and an addition operation.
4. The apparatus of claim 3 , wherein the multiplication operation means comprises:
a binary log generator that transforms the signals, which are sequentially input from the multiplexer, into binary logarithms and outputs the binary logarithms;
a shift left unit that doubles an output of the binary log generator and outputs a result; and
a binary inverse log generator that calculates inverse logarithm of the result output from the shift left unit.
5. The apparatus of claim 4 , further comprising an accumulating unit that sequentially adds output of the binary inverse log generator and outputs it as a NORM function value.
6. The apparatus of claim 5 , wherein the accumulating unit comprises:
an adder that combines a signal output from the binary inverse log generator and a specific input signal, and outputs a combination result; and
a register that receives feedback of a signal output from the adder and provides the specific input signal to the adder in synchronization with a specific clock signal.
7. The apparatus of claim 4 , further comprising a shift register that temporarily stores the binary logarithms output from the binary log generator and sequentially output a stored output.
8. The apparatus of claim 7 , wherein the division operation means comprises:
a NORM binary log generator that transforms the NORM function value, input from the accumulating unit, into a binary logarithm and outputs the binary logarithm;
a subtractor that subtracts the binary logarithm output from the NORM binary log generator from the stored output of the shift register, and outputs a subtraction result; and
a NORM binary inverse log generator that calculates binary inverse logarithm of the subtraction result and outputs a result.
9. The apparatus of claim 4 or 8 , wherein the binary log generator and the NORM binary log generator are embodied as a lookup table (LUT) or read-only memory (ROM).