SDRAM memory device with an embedded NAND flash controller
View Patent ↗A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.
1. A memory device comprising:
(a) a RAM operative to provide run-time execution functionality to a host, the RAM defined on a first die;
(b) a flash memory operative to store, for said host, code selected from the group consisting of an operating system, a pre-stored application, a downloaded application and user data, the flash memory defined on a second die, the flash memory capable of communicating directly with a host system using different signals that are distinct from signals communicated by the RAM;
(c) an interface for communicating with said host using only a RAM protocol; and
(d) a controller, of the flash memory, that is operative to exchange said code residing on the flash memory directly with said host using said RAM protocol independently of said RAM and without using said RAM, in support of said storing of said code, and that also is operative to exchange signals directly between said interface and said RAM in support of said run-time execution functionality, the controller fabricated on the first die alongside the RAM.
2. The memory device of claim 1 , wherein said flash memory is a NAND flash memory.
3. The memory device of claim 1 , wherein said RAM is an SDRAM.
4. The memory device of claim 1 , wherein said interface is a sole interface for communicating with said host.
5. An embedded device, comprising:
(a) a CPU;
(b) a memory device that includes:
(i) a RAM for providing run-time execution functionality to said CPU, said RAM defined on a first die,
(ii) a flash memory in which said CPU accesses code selected from the group consisting of an operating system, a pre-stored application, a downloaded application and user data, said flash memory defined on a second die that is distinct from the first die, the flash memory capable of communicating directly with a host system using different signals that are distinct from signals communicated by the RAM; and
(c) a communication link, whereby said CPU and said memory device communicate with each other using only signals of a RAM protocol; and
wherein said memory device further includes:
(iii) a controller, of the flash memory, that is operative to exchange said code residing on the flash memory directly with said CPU using said RAM protocol independently of said RAM and-without using said RAM, in support of said accessing of said code, and that also is operative to exchange said signals directly between said CPU and said RAM in support of said run-time execution functionality, the controller fabricated on the first die alongside said RAM.
6. A method of operating an embedded device that includes a CPU, a RAM, a flash memory and a controller of the flash memory, the method comprising the following steps performed by the CPU:
(a) using a RAM protocol to communicate with the RAM for run-time execution, wherein the RAM is defined on a first die;
(b) storing, in the flash memory, code selected from the group consisting of an operating system, a pre-stored application, a downloaded application and user data, wherein the flash memory is defined on a second die that is distinct from the first die, the flash memory capable of communicating directly with a host system using different signals that are distinct from signals communicated by the RAM; and
(c) using said RAM protocol to communicate with the controller for directly accessing said code in the flash memory, said code being accessed by the controller independently of the RAM and without using the RAM, wherein the controller is defined on the first die alongside the RAM.