IP Library Granted Patent US 7,937,554
Granted Patent B2
US 7,937,554 · App. 10/704,891 · Granted May 3, 2011

System and method for managing memory

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Quick Facts
Patent No.
US 7,937,554
App. No.
10/704,891
Granted
May 3, 2011
Kind
B2
Abstract

Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.

Claims (39)

1. A method for handling memory accesses by a user space application and a non-user space application, comprising:

advertising a memory region using at least one of a virtual address based tagged offset and a zero based tagged offset, the advertising of the memory region comprising advertising the memory region using a first base offset (FBO); and

inserting, via a lower layer protocol application or a device, information related to the FBO in a message advertising the memory region.

2. The method according to claim 1 , comprising:

storing the at least one of the virtual address based tagged offset and the zero based tagged offset in a common format in a memory management system.

3. The method according to claim 1 , comprising:

using a common set of memory management algorithms for an application using the virtual address based tagged offset or an application using the zero based tagged offset.

4. The method according to claim 1 , wherein an upper layer protocol application or an upper layer protocol device is unaware of the use of the FBO.

5. The method according to claim 1 , wherein the inserting is via the lower layer protocol application.

6. The method according to claim 1 , wherein the inserting is via the device.

7. The method according to claim 6 , wherein the device is a lower layer protocol device.

8. The method according to claim 6 , wherein the device is a remote direct memory access (RDMA) interface.

9. The method according to claim 6 , wherein the device is a network interface card.

10. The method according to claim 1 , wherein the advertising of the memory region uses the zero based tagged offset.

11. The method according to claim 1 , wherein the advertising of the memory region uses the virtual address based tagged offset.

12. The method according to claim 1 , wherein the lower layer protocol application uses RDMA.

13. The method according to claim 1 , wherein the advertising of the memory region uses the virtual address based tagged offset and the zero based tagged offset.

14. A method for handling memory accesses, comprising:

advertising a memory region using a zero based tagged offset, the advertising of the memory region comprising advertising the memory region using a first base offset (FBO); and

inserting, via a lower layer protocol application, information related to the FBO in a message advertising the memory region.

15. The method according to claim 14 , comprising:

storing a virtual address based tagged offset and the zero based tagged offset in a common format in a memory management system.

16. The method according to claim 14 , comprising:

using a common set of memory management algorithms for an application using a virtual address based tagged offset or an application using the zero based tagged offset.

17. The method according to claim 14 , wherein an upper layer protocol application or an upper layer protocol device is unaware of the use of the FBO.

18. The method according to claim 14 , wherein the advertising of the memory region uses the zero based tagged offset and the virtual address based tagged offset.

19. The method according to claim 14 , wherein the lower layer protocol application uses remote direct memory access (RDMA).

20. A method for handling memory accesses, comprising:

advertising a memory region using a zero based tagged offset, the advertising of the memory region comprising advertising the memory region using a first base offset (FBO); and

inserting, via a lower layer protocol device, information related to the FBO in a message advertising the memory region.

21. The method according to claim 20 , comprising:

storing a virtual address based tagged offset and the zero based tagged offset in a common format in a memory management system.

22. The method according to claim 20 , comprising:

using a common set of memory management algorithms for an application using a virtual address based tagged offset or an application using the zero based tagged offset.

23. The method according to claim 20 , wherein an upper layer protocol application or an upper layer protocol device is unaware of the use of the FBO.

24. The method according to claim 20 , wherein the advertising of the memory region uses the zero based tagged offset and the virtual address based tagged offset.

25. The method according to claim 20 , wherein the lower layer protocol device uses remote direct memory access (RDMA).

26. The method according to claim 20 , wherein the lower layer protocol device comprises an RDMA interface.

27. The method according to claim 20 , wherein the lower layer protocol device comprises a network interface card.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
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From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
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From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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From: BROADCOM CORPORATION
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2004
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To: BROADCOM CORPORATION
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