Semiconductor light emitting device and method
View Patent ↗A light-emitting device includes: a semiconductor structure formed on one side of a substrate, the semiconductor structure having a plurality of semiconductor layers and an active region within the layers; and first and second conductive electrodes contacting respectively different semiconductor layers of the structure; the substrate comprising a material having a refractive index n>2.0 and light absorption coefficient α, at the emission wavelength of the active region, of α>3 cm −1 . In a preferred embodiment, the substrate material has a refractive index n>2.3, and the light absorption coefficient, α, of the substrate material is α<1 cm −1 .
1. A method for making semiconductor light emitting device chips, comprising the steps of:
providing a substrate of substantially transparent silicon carbide;
forming a semiconductor structure on one side of said substrate, said semiconductor structure having a plurality of semiconductor layers and an active region within said layers;
applying electrodes to semiconductor layers of said structure on said one side of said substrate to four semiconductor light emitting devices; and
dicing said substrate and devices into a plurality of chips
wherein said substrate has a refractive index n>2.3 and a light absorption coefficient α, at an emission wavelength of said active region, of α<3 cm −1 .
2. The method as defined by claim 1 , further comprising bonding the electrodes of each device chip to a submount to obtain inverted semiconductor light emitting devices.
3. The method as defined by claim 1 , wherein said step of dicing includes sawing of said substrate and devices into a plurality of chips.
4. The method as defined by claim 1 , wherein said step of providing a substrate comprises providing a substrate of polycrystalline silicon carbide.
5. The method as defined by claim 1 , wherein said step of providing a substrate comprises providing a substrate of polycrystalline silicon carbide having single crystal silicon carbide thereon.
6. The method as defined by claim 1 , wherein said step of dicing into chips comprises dicing into chips having at least one dimension perpendicular to thickness that is less than 400 μm.
7. The method as defined by claim 1 , wherein said step of dicing into chips comprises dicing into chips having dimensions perpendicular to thickness that are less than 400×400 μm.
8. The method as defined by claim 1 , wherein step of dicing into chips comprises dicing into chips having an area less than 0.16 mm 2 .
9. The method as defined by claim 1 , wherein said step of dicing into chips comprises dicing into chips having at least one dimension perpendicular to thickness that is less than 300 μm.
10. The method as defined by claim 1 , wherein said step of dicing into chips comprises dicing into chips having dimensions perpendicular to thickness that are less than 300×300 μm.
11. The method as defined by claim 1 , wherein step of dicing into chips comprises dicing into chips having an area less than 0.09 mm 2 .
12. The method as defined by claim 1 , wherein said step of forming a semiconductor structure having a plurality of layers comprises providing a plurality of layers including an n-type layer of a III-nitride semiconductor and a p-type layer of a III-nitride semiconductor on opposing sides of said active region.
13. The method as defined by claim 9 , wherein said step of forming a semiconductor structure having a plurality of layers comprises providing a plurality of layers including an n-type layer of a III-nitride semiconductor and a p-type layer of a III-nitride semiconductor on opposing sides of said active region.