IP Library Granted Patent US 7,157,731
Granted Patent B2
US 7,157,731 · App. 10/707,525 · Granted Jan 2, 2007

Semiconductor device and its manufacture

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Quick Facts
Patent No.
US 7,157,731
App. No.
10/707,525
Granted
Jan 2, 2007
Kind
B2
Abstract

In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.

Claims (9)

1. A semiconductor device, comprising:

a semiconductor substrate including first and second areas;

a plurality of first conductive patterns formed in the first area;

a plurality of second conductive patterns formed in the second area, said second conductive pattern having a structure different from said first conductive pattern;

first, second, third and fourth insulating films formed on said second conductive pattern, first insulating film having a same pattern as said second conductive pattern, said second, said third and fourth insulating films having a different pattern from said second conductive pattern; and

fifth and sixth insulating films made of same materials as said third and fourth insulating films, formed directly on the first conductive pattern, and having a different pattern from said first conductive pattern.

2. A semiconductor device according to claim 1 , further comprising side spacers formed on side walls of said first conductive pattern, said side spacer made of same material as said second insulating film.

3. A semiconductor device according to claim 2 , further comprising:

first source/drain regions formed in a surface layer of said semiconductor substrate on both sides of each said first conductive pattern, said first source/drain regions formed with a silicide layer; and second source-drain regions formed in a surface layer of said semiconductor substrate on both sides of each said second conductive pattern, said second source/drain regions not formed with a silicide layer.

Assignments (3)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Aug 2, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024804/0269 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0876 →