Integrated circuit with reduced analog coupling noise
View Patent ↗In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5 - 1, 5 - 2 , and 5 - 3 connected thereto not to overlap on the layout, the analog lines 5 - 1 and 5 - 2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3 . Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5 - 1 and 5 - 2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5 - 1 and 5 - 2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5 - 1 and 5 - 2 can be suppressed.
1. A semiconductor integrated circuit, comprising on the same chip:
a plurality of circuit blocks composed by the CMOS process, which have ON/OFF functions of a power source;
a control circuit to control the ON/OFF functions of the power source of said plurality of circuit blocks; and
analog control lines connected between said plurality of circuit blocks and said control circuit;
wherein said analog control lines are wired on the layout of a certain circuit block;
when the power source of said certain circuit block is turned ON by said control circuit, said another circuit block is not controlled in a state of being ON simultaneously therewith.
2. A semiconductor integrated circuit, comprising:
a single chip;
first and second CMOS circuit blocks arranged on the single chip;
a control circuit that at least controls ON/OFF functions of each of the first and second CMOS circuit blocks; and
analog control lines connected between said each of the first and second CMOS circuit blocks and said control circuit;
wherein said analog control lines are arranged over a layout of at least one of the first and second CMOS circuit blocks,
wherein said control circuit controls analog processes in each of the first and second CMOS circuit blocks in a manner that suppresses mutual interference between the first CMOS circuit block and the second CMOS circuit block.
3. The semiconductor integrated circuit of claim 2 , wherein the control circuit is located on the single chip.
4. The semiconductor integrated circuit of claim 2 , wherein the control circuit controls power applied to each of the first and second CMOS circuit blocks in a manner that ensures that when the first CMOS circuit block is powered, the second CMOS circuit block remains unpowered.