Distributed system and method for the remote acquisition of data in packets with a communication protocol which optimizes the transmission speed
View Patent ↗The invention comprises several vehicle parameters transducers ( 1, 2, 3, 4 ) associated to respective slave circuits ( 10, 20, 30, 40 ) connected by a single, time-shared serial bus ( 60 ) with a master slave ( 50 ) which, when activated from a digital processing unit (DP), performs a communication with each one of the slave circuits, a bit frame circulating through said serial bus ( 60 ) according to a transmission protocol, without error correction, formed by a series of bit packets, each one with information from a corresponding slave circuit and separated by a short time interval, which information is stored in said master circuit ( 50 ) from where it is acquired by the (DP) through a parallel bus ( 70 ).
1. A distributed system for acquiring remote data in packets with a communication protocol optimizing the transmission speed, particularly applicable to the follow-up and control in an automotive vehicle of the values of signals provided by a series of transducer devices distributed in different parts of the vehicle and which follow different analog or digital values, characterized in that: said transducer devices are associated to respective slave/subordinate circuits which are connected, through a single, time-shared serial communications bus, to a master/main circuit, which in turn is connected to a digital processing unit through a parallel bus, each one of said slave circuits and master circuit being provided with a respective digital processor and a respective transceiver device, and which master circuit is provided so as to perform, upon petition of an activation by said unit, a repetitive or non-repetitive consultation, setting up communication with each one of the slave/subordinate circuits according to a communication protocol without error correction which includes a series of bit packets, each one of which comprises:
a start bit with a longer duration/length than the data bits so that it is fully identified;
1.5 delay/synchronism bits for the frames going from master to slave;
one or more address bits, indicative of the slave/subordinate circuit to be consulted; and
several data bits containing information coming from the consulted slave/subordinate circuit.
2. A system according to claim 1 , characterized in that said start bit of each bit packet, with a longer duration/length than the data bits, is provided so as to generate a reinitialization of all the slave/subordinate circuits.
3. A system according to claim 1 , characterized in that said start bit of each bit packet has a duration of at least two times that of each one of the data bits of the packet.
4. A system according to claim 1 , characterized in that each bit of the packet in address, data or error detection functions, is encoded in Manchester format.
5. A system according to claim 1 , characterized in that each bit packet includes an additional protocol error detection bit in the data field or address field.
6. A system according to claim 5 , characterized in that said error detection bit is the last one of each packet.
7. A system according to claim 1 , characterized in that a short time interval of separation between bit packets circulating through the serial bus is comprised within a range of 0 to 1 bit.
8. A system according to claim 1 , characterized in that said serial bus is formed by a twisted differential cable comprising two twisted insulated copper conductors in shunt with a ground line.
9. A system according to claim 1 , characterized in that said serial bus is formed by a single insulated copper conductor in shunt with a ground line.
10. A system according to claim 1 , characterized in that each one of those transducer devices providing an analog signal is associated to an A/D converter connected to the corresponding slave/subordinate circuit transceiver.
11. A system according to claim 1 , characterized in that said digital processing unit is linked to another bus of the vehicle, such as a CAN or other type of bus.
12. A system according to claim 1 , characterized in that each bit packet contains, in addition to said one or more address bits, data bits susceptible to being transmitted from the master circuit to the consulted slave/subordinate circuit, such that they are univocally recognized by said slave/subordinate circuits.
13. A process for acquiring remote data in packets with a communication protocol optimizing the transmission speed, particularly applicable to the follow-up and control in an automotive vehicle of the values of signals provided by a series of transducer devices distributed in different parts of the vehicle and which follow different analog or digital values, integrated in a system according to claim 1 , characterized in that:
said master circuit, upon petition of the application thereto of a signal emitted by said digital processing unit, performs a repetitive or non-repetitive consultation of each one of the slave/subordinate circuits through the parallel bus, setting up communication with them through said time-shared serial bus by means of said bit packets according to said transmission protocol without error correction;
the slave/subordinate circuits transmit said data bits in response to said consultation, which data are stored in said master circuit in arrayed entries;
the master circuit sends an interruption order through a parallel bus, by means of the activation of a signal, to the digital processing unit indicative of the end of the consultation cycle; and
the digital processing unit acquires, by means of the activation of a reading order, the data bits stored in the master circuit while the system continues with a new consultation communication between the master circuit and the slave/subordinate circuits.
14. A process according to claim 13 , characterized in that said consultation cycles between master circuit and slave/subordinate circuits and acquisition of data stored in the master circuit from the digital processing unit are carried out cyclically at a predetermined frequency imposed by said digital processing unit.
15. A process according to claim 13 , characterized in that those bit packets whose transmission has been detected as erroneous by means of said error detection bit are skipped over, passing to the next bit packets.