Method and system for maintaining uniform module junction temperature during burn-in
View Patent ↗A method for controlling the burn-in temperature of a semiconductor chip includes determining a DC current of the chip, and determining a difference between the DC current and a target current, the target current being selected to produce a desired chip temperature. An operating frequency of the chip is calculated, based on the determined difference between the DC current and the target current, so as generate an additional AC component of current to attain the target current.
1. A method for controlling the burn-in temperature of a semiconductor chip, the method comprising:
determining a DC current of the chip;
determining a difference between said determined DC current and a target current, said target current selected to produce a desired chip temperature; and
calculating an operating frequency of the chip, based on said determined difference between said DC current and said target current, so as generate an additional AC component of current to attain said target current.
2. The method of claim 1 , wherein said DC current is a leakage current of the chip.
3. The method of claim 2 , further comprising measuring said DC leakage current of the chip and recording the measured value on the chip.
4. The method of claim 3 , wherein said DC leakage current is encoded within on-chip fuse registers.
5. The method of claim 4 , wherein said target current is also encoded within on-chip fuse registers.
6. The method of claim 2 , wherein said calculated operating frequency is implemented through clock multiplication circuitry included within the chip.
7. The method of claim 2 , wherein said calculating an operating frequency further comprises multiplying an external clock signal by a multiplication factor, said multiple based on a cycle time of said external clock signal, said determined difference between said DC leakage current and said target current, an internal chip capacitance, and a chip operating voltage.
8. The method of claim 7 , wherein said multiplication factor is determined in accordance with the following expression:
Cycle Burnin ·(I Burnin −I DD )/(C·V DD );
wherein Cycle Burnin is said cycle time of said external clock signal, I Burnin is said target current, I DD is said measured DC leakage current, C is said internal chip capacitance, and V DD is said chip operating voltage.
9. The method of claim 8 , further comprising:
generating an internal clock signal by multiplying said external clock signal by said multiplication factor; and selectively switching between said external clock signal and said internal clock signal as an input clock signal to devices on the chip, depending on whether the chip is in a burn-in mode.
10. The method of claim 8 , wherein said multiplication factor is encoded on the chip.
11. A system for controlling the burn-in temperature of a semiconductor chip, comprising:
a processing device on the chip for determining a difference between a DC current of the chip and a target current, said target current selected to produce a desired chip temperature; and
said processing device further configured for calculating an operating frequency of the chip, based on said determined difference between said DC current and said target current, so as generate an additional AC component of current to attain said target current.
12. The system of claim 11 , wherein said DC current is a leakage current of the chip.
13. The system of claim 12 , wherein said DC leakage current is encoded within on-chip fuse registers.
14. The system of claim 12 , wherein said calculated operating frequency is further implemented through clock multiplication circuitry included within the chip.
15. The system of claim 14 , wherein said operating frequency is calculated by multiplying an external clock signal by a multiplication factor, said multiplication factor based on a cycle time of said external clock signal, said determined difference between said DC leakage current and said target current, an internal chip capacitance, and a chip operating voltage.
16. The system of claim 15 , wherein said multiplication factor is determined in accordance with the following expression:
Cycle Burnin ·(I Burnin −I DD )/(C·V DD );
wherein Cycle Burnin is said cycle time of said external clock signal, I Burnin is said target current, I DD is said measured DC leakage current, C is said internal chip capacitance, and V DD is said chip operating voltage.
17. The system of claim 16 , further comprising:
an internal clock signal generated by said clock multiplication circuitry; and
a switching device for selectively switching between said external clock signal and said internal clock signal as an input clock signal to devices on the chip, depending on whether the chip is in a burn-in mode.
18. The system of claim 16 , wherein said multiplication factor is encoded on the chip.
19. The system of claim 14 , wherein said target current is also encoded within on-chip fuse registers.