IP Library Granted Patent US 7,310,120
Granted Patent B2
US 7,310,120 · App. 10/711,581 · Granted Dec 18, 2007

Receiver of analogue video signal having means for analogue video signal conversion and method for control of display of video frames

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Quick Facts
Patent No.
US 7,310,120
App. No.
10/711,581
Granted
Dec 18, 2007
Kind
B2
Abstract

A receiver of analogue video signal having means for analogue video signal conversion has a receiving block ( 201 ) for receiving a first analogue video signal, a conversion block ( 202 ) for conversion of the first analogue signal into a digital signal, a buffer controller ( 203 ) of frame buffers, a video coder ( 204 ) for transforming the digital signal into an analogue signal of a second format, a receiver ( 205 ) for displaying the analogue signal of a second format and a processor ( 206 ) for data processing and controlling the receiving block, the conversion block, the buffer controller, the video coder and the receiver. The buffers controller ( 203 ) has three modules, namely, buffers ( 203 b ) linked together, a decoding frame controller ( 203 a ) and a displaying frame controller ( 203 c ). Certain frames in this device will be omitted when the output frames frequency is lower than the input frequency and displayed more than once when the output frames frequency is higher than the input frequency.

Claims (46)

1. A receiver of analogue video signal having means for analogue video signal conversion comprising

a receiving block for receiving a first analogue video signal of a first format;

a conversion block for conversion of the first analogue signal of the first format into a digital signal and connected to the receiving block;

a buffer controller of frames included in the digital signal connected to the conversion block and having frame buffers organized as a two-way list, a decoding frame controller and a displaying frame controller;

a video coder for transforming the digital signal into a second analogue signal of a second format;

a receiver for displaying the second analogue signal of the second format; and

a processor for data processing and controlling the receiving block, the conversion block, the buffer controller, the video coder and the receiver.

2. A method for control of display of video frames comprising the steps of:

creating at least three frame buffers organized as a two-way list;

setting a current decoder buffer chosen from the frame buffers;

fetching of data of frames from a first analogue video signal of a first format;

temporarily storing the data of the frames in the current decoder buffer;

setting a display buffer chosen from the frame buffers; and

reading data of a display frame from the display buffer and displaying the frame in a second video format.

3. The method according to claim 2 , wherein the last element of the two-way list is linked to the first element of the two-way list.

4. The method according to claim 2 , wherein the step of fetching and the storing of the data of the frames comprises the steps of

setting the current decoder buffer, to which the data of the frames will be decoded, to a first free buffer from the frame buffers;

awaiting for a bottom vertical synchronization signal in the first analogue video signal of the first format;

checking if a next buffer, in relation to the current decoder buffer, is being displayed, after the bottom vertical synchronization signal is detected;

setting the next buffer as the current decoder buffer when the next buffer is not being displayed;

detecting a top vertical synchronization signal in the first analogue video signal of the first format;

decoding of the data of the frame to the current decoder buffer; and

returning to the awaiting for the bottom vertical synchronization signal in the input video signal.

5. The method according to claim 2 , wherein the step of reading and displaying data comprises the steps of

awaiting for an appearance of a bottom vertical synchronization signal in an analogue output video signal;

setting a previous buffer in relation to the current decoder buffer as the display buffer after appearance of a bottom vertical synchronization signal;

awaiting for a top synchronization signal in the output video signal;

displaying the display buffer after detecting the top vertical synchronization signal in the output video signal; and

returning to the awaiting for the bottom vertical synchronization signal in the output video signal.

6. A method for control of display of video frames comprising the steps of:

applying at least three frame buffers;

setting a current decoder buffer chosen from the frame buffers;

fetching of data of a frame from a first analogue video signal;

awaiting for a bottom vertical synchronization signal in the first analogue video signal;

checking if a next buffer, in relation to the current decoder buffer, is being displayed, after the bottom vertical synchronization signal is detected;

setting the next buffer as the current decoder buffer when the next buffer is not being displayed;

detecting a top vertical synchronization signal in the first analogue video signal;

decoding of the data of the frame to the current decoder buffer;

temporarily storing the data of the frame in the current decoder buffer;

returning to the awaiting for the bottom vertical synchronization signal in the first analogue video signal;

awaiting for an appearance of a bottom vertical synchronization signal in an analogue output video signal;

setting a previous buffer in relation to the current decoder buffer as the display buffer after appearance of the bottom vertical synchronization signal;

awaiting for a top synchronization signal in the analogue output video signal;

displaying the display buffer after detecting the top vertical synchronization signal in the analogue output video signal; and

returning to the awaiting for the bottom vertical synchronization signal in the analogue output video signal.

7. The method according to claim 6 , wherein the frame buffers are organized in a two-way list and wherein the last element of the two-way list is linked to the first element of the two-way list.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2020
From: ADVANCED DIGITAL BROADCAST S.A.
To: EQUITABLE IP HOLDINGS LLC
Reel/Frame 052191/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2020
From: EQUITABLE IP HOLDINGS, LLC
To: ANADEX DATA COMMUNICATION LLC
Reel/Frame 052192/0046 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2009
From: ADVANCED DIGITAL BROADCAST POLSKA SP. Z O.O.; ADVANCED DIGITAL BROADCAST LTD.
To: ADVANCED DIGITAL BROADCAST S.A.
Reel/Frame 023254/0148 →
SECURITY INTEREST Recorded Sep 27, 2004
From: ADVANCED DIGITAL BROADCAST POLSKA SP. Z O.O.
To: DIGITAL BROADCAST LTD., ADVANCED
Reel/Frame 015181/0332 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2004
From: ZALEWSKI, MARCIN
To: ADVANCED DIGITAL BROADCAST POLSKA SP. Z O.O.
Reel/Frame 015181/0335 →