Structure and method for making strained channel field effect transistor using sacrificial spacer
View Patent ↗A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
1. A field effect transistor (“FET”), comprising:
a single-crystal semiconductor region of a substrate, said single-crystal semiconductor region having a first composition;
a gate overlying said single-crystal semiconductor region;
a pair of first spacers overlying respective opposite sidewalls of said gate;
a pair of regions consisting essentially of a single-crystal semiconductor alloy having a second composition different from said first composition, said semiconductor alloy regions disposed on opposite sides of said gate, each said semiconductor alloy region spaced a first distance from said gate; and
a source region and a drain region at least partly disposed in respective ones of said semiconductor alloy regions, each of said source region and said drain region being spaced a second distance from said gate of, said second distance being different from and independent from said first distance, said second distance being at least partly determined by spacings of said first spacers from said sidewalls of said gate.
2. The FET as claimed in claim 1 , wherein said second distance is greater than said first distance.
3. The FET as claimed in claim 2 , wherein said single-crystal semiconductor region consists essentially of silicon and said semiconductor alloy regions consist essentially of silicon germanium.
4. The FET as claimed in claim 3 , wherein said silicon germanium regions are at least partly disposed in trenches disposed in said single-crystal silicon region.
5. The FET as claimed in claim 4 , wherein said substrate is a silicon-on-insulator (SOI) substrate and said single-crystal silicon region is disposed above a buried oxide layer of said SOI substrate.
6. The FET as claimed in claim 5 , wherein said silicon germanium regions have bottom edges disposed at a depth of about 80% or greater of a depth of a top of said buried oxide layer from a top surface of said single-crystal silicon region.
7. The FET as claimed in claim 6 , wherein the depth of said bottom edges is about 90% of the depth of said top of said buried oxide layer.
8. The FET as claimed in claim 7 , further comprising extension regions underlying said first spacers and at least partly underlying said gate stack.
9. The FET as claimed in claim 8 , further comprising halo regions underlying said first spacers and at least partly underlying said gate stack.
10. The FET as claimed in claim 8 , wherein said sidewalls of said gate stack are oxidized, wherein said first spacers are disposed over said oxidized sidewalls.
11. The FET as claimed in claim 10 , further comprising forming second spacers disposed laterally outward from said first spacers.
12. The FET as claimed in claim 11 , further comprising silicide regions overlying said silicon germanium regions, wherein said silicide regions are spaced a distance from said gate at least partly determined by spacings of said second spacers from said gate.
13. The FET as claimed in claim 12 , wherein said gate includes a gate silicide region and a polycrystalline semiconductor region, said gate silicide region overlying and self-aligned to said polycrystalline semiconductor region.
14. The FET as claimed in claim 1 , wherein said second distance is less than said first distance.
15. The FET as claimed in claim 1 , wherein said single-crystal semiconductor alloy includes at least two semiconductor materials and a percentage amount of at least one of said semiconductor materials varies between said first and second compositions.
16. A field effect transistor (“FET”), comprising:
a single-crystal silicon region of a silicon-on-insulator substrate;
a gate overlying said single-crystal silicon region;
a pair of first spacers disposed over opposite sidewalls of said gate;
a pair of regions consisting essentially of single-crystal silicon germanium disposed on opposite sides of said gate, each said silicon germanium region spaced a first distance from said gate;
a source region and a drain region at least partly disposed in respective ones of said silicon germanium regions, each of said source region and said drain region being spaced a second distance from said gate, said second distance being different from and independent from said first distance, said second distance being at least partly determined by spacings of said first spacers from said sidewalls of said gate; and
silicide regions, at least one of said silicide regions overlying a semiconductor portion of said gate and said silicide regions at least partly overlying said silicon germanium regions.