IP Library Granted Patent US 7,301,846
Granted Patent B2
US 7,301,846 · App. 10/711,653 · Granted Nov 27, 2007

Method and apparatus for increasing computer memory performance

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,301,846
App. No.
10/711,653
Granted
Nov 27, 2007
Kind
B2
Abstract

A method and apparatus for providing power to a memory array of a computer's memory subsystem, and more particularly power at a level greater than that available through the computer motherboard so as to boost memory performance and operational stability. The apparatus includes a supply device for supplying an input voltage to the memory subsystem at a level that is higher than the power level provided to the memory subsystem by the motherboard. The method entails electrically connecting the supply device to the memory subsystem, and then electrically connecting a power source to the device to deliver the input voltage to the memory subsystem. The additional input voltage supplied to the memory subsystem causes memory chips on memory modules of the memory subsystem to run at higher frequencies, such that the various internal operations of the memory, such as reading and writing, occur more quickly.

Claims (39)

1. An apparatus for increasing power to at least one memory module in at least a first of a plurality of memory slots of a memory subsystem associated with a motherboard of a computer, the apparatus comprising means for supplying an input voltage to the memory module of the memory subsystem at a level that is higher than a power level provided to the memory subsystem by the motherboard, the input voltage supplying means having a portion configured to plug directly into an available second memory slot of the memory subsystem and is thereby linked to a memory bus of the memory subsystem to deliver the input voltage to the memory module in the first memory slot.

2. The apparatus according to claim 1 , wherein the higher level of the input voltage is such that memory performance of the memory subsystem is improved by causing memory chips on the memory module to run at higher frequencies.

3. The apparatus according to claim 1 , wherein the input voltage is in excess of available voltage present on a motherboard within the computer.

4. The apparatus according to claim 1 , wherein the input voltage is in excess of 3.3 volts.

5. The apparatus according to claim 1 , wherein the apparatus further comprises cable means that delivers a supply voltage from a power source to the input voltage supplying means.

6. The apparatus according to claim 5 , wherein the power source is external of the computer and comprises an AC/DC converter.

7. The apparatus according to claim 5 , wherein the power source is external of the computer and comprises a DC power source.

8. The apparatus according to claim 5 , wherein the power source is a power supply unit within the computer.

9. The apparatus according to claim 5 , wherein the power source supplies at least five volts to the input voltage supplying means.

10. The apparatus according to claim 1 , wherein the second memory slot is on a motherboard of the computer.

11. The apparatus according to claim 1 , wherein the input voltage supplying means comprises at least a first printed circuit board and the portion of the input voltage supplying means comprises electrical pins along an edge of the first printed circuit board, the edge of the first printed circuit board being configured to be received in the second memory slot and the pins being configured for making electrical contact with the second memory slot.

12. The apparatus according to claim 11 , wherein the input voltage supplying means further comprises means for displaying the input voltage delivered by the input voltage supplying means to the memory subsystem, the displaying means not being located on the first printed circuit board.

13. The apparatus according to claim 11 , wherein the input voltage supplying means further comprises means for adjusting the input voltage delivered by the input voltage supplying means to the memory subsystem, the adjusting means not being located on the first printed circuit board.

14. The apparatus according to claim 1 , wherein the input voltage supplying means comprises means for displaying the input voltage delivered by the input voltage supplying means to the memory subsystem.

15. The apparatus according to claim 1 , wherein the input voltage supplying means comprises means for adjusting the input voltage delivered by the input voltage supplying means to the memory subsystem.

16. The apparatus according to claim 1 , wherein the memory subsystem comprises DIMM memory modules.

17. A method of providing power to at least one memory module in at least a first of a plurality of memory slots of a memory subsystem of a computer, the method comprising the steps of:

electrically connecting a supply means to an available memory slot of the memory subsystem;

electrically connecting a power source to the supply means so that the supply means generates an input voltage; and

delivering the input voltage to the memory module through a memory bus of the memory subsystem to deliver the input voltage to the memory module in the first memory slot.

18. The method according to claim 17 , wherein the input voltage is in excess of available voltage present on a motherboard within the computer.

19. The method according to claim 17 , wherein the input voltage is in excess of 3.3 volts.

20. The method according to claim 17 , wherein the power source is external of the computer.

21. The method according to claim 17 , wherein the power source is a power supply unit within the computer.

22. The method according to claim 17 , wherein the power source supplies at least five volts to the supply means.

23. The method according to claim 17 , wherein the available memory slot is on a motherboard of the computer.

24. The method according to claim 17 , further comprising the step of displaying the input voltage delivered by the supply means to the memory subsystem.

25. The method according to claim 17 , further comprising the step of adjusting the input voltage delivered by the supply means to the memory subsystem.

26. The method according to claim 25 , wherein the adjusting step comprises the steps of:

rebooting the computer after the electrically connecting;

entering the BIOS of the computer;

adjusting the input voltage delivered by the supply means to the memory subsystem whereupon the supply means delivers the input voltage to the memory subsystem; and then

saving and exiting the BIOS.

27. The method according to claim 25 , wherein the adjusting step is performed during operation of the computer.

28. The method according to claim 25 , wherein the adjusting step is performed during system idle of the computer.

29. The method according to claim 25 , wherein the adjusting step is performed when the computer is off.

30. The method according to claim 17 , wherein the step of electrically connecting the supply means to the available memory slot comprises physically installing the supply means into the available memory slot.

31. The method according to claim 17 , wherein the memory subsystem comprises DIMM memory modules.

32. The method according to claim 17 , wherein the step of electrically connecting the supply means to the available memory slot does not comprise physically installing the supply means into the available memory slot but instead comprises using a separate interface means to electrically couple the supply means and the memory subsystem.

Assignments (18)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF RECEIVING PARTY PREVIOUSLY RECORDED ON REEL 015473 FRAME 0474 Recorded Mar 28, 2006
From: PETERSEN, RYAN M.; NELSON, ERIC L.
To: OCZ TECHNOLOGY GROUP INC.
Reel/Frame 017394/0675 →
CORRECTIVE ASSIGNMENT TO CORRECT NAME OF CONVEYING PARTY Recorded Mar 9, 2006
From: OCZ TECHNOLOGY GROUP INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 017330/0571 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2005
From: OCZ TECHNOLOGY
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 016187/0892 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2004
From: PETERSEN, RYAN M.; NELSON, ERIC L.
To: OCZ TECHNOLOGY
Reel/Frame 015473/0474 →