Memory controller and data processing system
View Patent ↗A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
1. A semiconductor device comprising: a memory controller receiving commands from a CPU, and controlling a memory including a plurality of memory banks, wherein said memory controller has a first mode and a second mode, wherein each of said plurality of memory banks comprises a plurality of word lines, data lines, and memory cells, wherein said memory is controlled to precharge after a read access in said first mode, wherein said memory is controlled to receive next access command without precharge operation after a read access in said second mode, wherein when a refresh command is received by said memory controller, said memory controller precharges said plurality of memory cells of said plurality of memory banks before refreshing said plurality of memory cells,
wherein a successive read access after refresh command is operated without a precharge operation,
wherein said memory controller comprises a page access decision circuit, a mode changing circuit, and an address generating circuit, wherein said page decision circuit compares a row address inputted to said memory controller and the previous address, wherein said mode changing circuit receives signals from said page decision circuit and holds information of a number of consecutive access to each of said plurality of said memory banks, and wherein said address generating circuit receives signals from said page decision circuit and from said mode changing circuit and outputs bank active commands, bank addresses, row addresses, and column addresses to said memory.
2. The semiconductor device according to claim 1 , wherein said memory controller further comprises a first and a second bus coupled to said address generating circuit, wherein said first bus is used for transferring commands and said second bus is used for transferring addresses.
3. The semiconductor device according to claim 1 , wherein said memory is a SDRAM.
4. The semiconductor device according to claim 2 , further comprising: a DRAM memory chip to be controlled by said memory controller, wherein said DRAM memory chip is molded in the same package as the memory controller.
5. The semiconductor device according to claim 2 , wherein during said first mode if an access to a same word line continues, a precharge operation before a read operation is abridged, wherein during said second mode if an access to a different word line occurs, a precharge is operated before a read operation.