Line address computer for providing coefficients to a chroma filter

1. A decoder system for displaying pictures, said method comprising:

a video decoder for decoding a picture, the decoded picture having a decode format;

a chroma filter for interpolating chroma pixels for a display format;

a line address computer for providing a set of weights to the chroma filter, the set of weights comprises a first set if the decode format comprises a first format, and a second set of weights to the display engine, if the decode format comprises a second format;

a first chroma line buffer for storing a row of displayed chroma Cr pixels;

a second chroma line buffer for storing a row of chroma Cb pixels; and

wherein the chroma line buffer:

receives an input for receiving another row of chroma Cr pixels;

interpolates a row of chroma Cr pixels for the display format based on the stored row of chroma Cr pixels, the received row of chroma Cr pixels, and the provided set of weights, thereby resulting in an interpolated row of chroma Cb pixels; and

provides the row of chroma Cb pixels stored in the second chroma line buffer with the interpolated row of chroma Cb pixels for display; and

wherein the chroma filter interpolates the chroma pixels for the display format based on the provided set of weights.

2. The decoder system of claim 1 , wherein the line address computer provides a third set of weights to the chroma filter, wherein the decode format comprises a third format.

3. The decoder system of claim 1 , wherein the first format, and the second format are selected from a group consisting of DV-25, TMS, and MPEG 4:2:0, and wherein the display format is 4:2:2.

4. The decoder system of claim 1 , wherein the decoder system further comprises:

a chroma line buffer for storing a row of top chroma pixels; and

wherein the chroma filter further comprises:

a first multiplier for multiplying the row of top chroma pixels with a first one of the set of weights;

a second multiplier for multiplying a bitstream comprising a row of bottom pixels with a second one of the set of weights; and

an adder for adding the product from the first multiplier and the product from the second multiplier.

5. The decoder system of claim 4 , wherein:

the chroma line buffer stores the bottom pixels from the bitstream;

the first multiplier multiplies the bottom pixels stored in the chroma line buffer with the first one of the set of weights;

the second multiplier multiplies another row of chroma pixels from the bitstream with the second one of the weights;

the adder adds the products of the first multiplier and the second multiplier, thereby generating another row of chroma pixels for the display format.

6. The decoder system of claim 1 , wherein the second chroma line buffer overwrites the chroma Cb pixels with the received another row of chroma Cb pixels.

7. The decoder system of claim 6 , wherein the chroma filter:

receives a row of Cb pixels; and

interpolates another row of Cb from the row of chroma Cb pixels stored in the local memory and the another row of chroma Cb pixels received.

8. A circuit for interpolating chroma pixels, said circuit comprising:

an input configured to receive an input bitstream;

a first chroma line buffer connected to the input, and configured to store at least a portion of the input bitstream;

a second chroma line buffer connected to the input and configured to store at least a portion of the input bitstream;

a first multiplexer with inputs, a first of the inputs connected to the first chroma line buffer, a second of the inputs connected to the second chroma line buffer, and a third of the inputs connected to the input configured to receive an input bitstream, the first multiplexer configured to select a particular one of the inputs as an output; and

a second multiplexer with inputs, a first of the inputs connected to the first chroma line buffer, a second of the inputs connected to the second chroma line buffer, and a third of the inputs connected to the input configured to receive an input bitstream, the second multiplexer configured to select a particular one of the inputs as an output.

9. The circuit of claim 8 , further comprising:

a first multiplier connected to the output of the first multiplexer, the first multiplier receiving a first weight from a line address computer and providing a product of the first weight and the output of the first multiplexer; and

a second multiplier connected to the output of the second multiplexer, the second multiplier receiving a second weight from the line address computer and providing a product of the first weight and the output of the first multiplexer.

10. The circuit of claim 9 , further comprising:

an adder connected to the first multiplier and the second multiplier, the adder configured to add the product of the first multiplier to the product of the second multiplier.