Multibit metal nanocrystal memories and fabrication
View Patent ↗Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 10 6 s, and provide 2-bit-per-cell storage capability.
1. A multibit storage cell, comprising:
a semiconductor substrate having source and drain regions separated by a channel region;
an insulator material formed on said substrate and having a plurality of metal nanocrystals embedded therein, said metal nanocrystals including a first portion forming a first storage element located in the region of a source side junction with said channel and a second portion forming a second storage element located in the region of a drain side junction with said channel;
a gate electrode on said insulator material;
a control layer formed in said insulator material between said gate electrode and said metal nanocrystals;
a tunnel layer formed between said metal nanocrystals and said substrate; and
bias voltages connected to said source and drain regions to produce asymmetric charging of said nanocrystals, wherein said metal nanocrystals are formed from a metal that is selected to have a work function value which affects transport of charge through said insulating material such that a first, low potential barrier is formed across said tunnel oxide during writing to said storage elements, and a second, higher potential barrier is formed across said tunnel oxide during retention of charge in said storage elements.
2. The storage cell of claim 1 , wherein said gate electrode overlies said nanocrystals and said channel.
3. The storage cell of claim 1 , wherein said bias voltages are connected to write and to read multiple bits of data in said storage elements.
4. The storage cell of claim 3 , wherein said bias voltages include write voltages selected to independently write data to said first and second storage elements.
5. The storage cell of claim 3 , wherein said bias voltages include read voltages selected to independently read data from said first and second storage elements.
6. The storage cell of claim 3 , wherein said bias voltages include first and second write voltages connectable to said source and drain to write information to said first storage element, and being reversible to write information to said second storage element.
7. The storage cell of claim 5 , wherein said bias voltages further include first and second read voltages connectable to said source and drain to read information written to said first storage element, and reversible to read information written to said second storage element.