Layout of a thin film transistor and the forming method thereof
View Patent ↗A transistor that at least has one of the following characteristics: First, the gate electrode is located outside the gate line, such that the whole transistor is located outside the gate line. Second, the projection of the semiconductor layer on the substrate is totally located inside the projection of the gate electrode on the substrate. Third, the drain cross the gate electrode, such that the projection of the cross-section is totally located inside the projection of the gate electrode. Final, the separated distance between the gate line, the gate electrode, the drain and the source is adjusted to let the variation of each of Cgd and Cds be not obviously affected by the alignment deviation.
1. A transistor, composing,
a first conducting structure upon a substrate;
a second conducting structure upon said substrate, with the projection of said second conducting structure onto said substrate intersecting the projection of said first conducting structure onto said substrate;
a third conducting structure upon said substrate contacting with said first conducting structure, with the projection of said third conducting structure onto said substrate completely inside said projection of said second conducting structure onto said substrate; and
a fourth conducting structure upon said substrate, with the projection of said fourth conducting structure onto said substrate separated from said projection of said first and said third conducting structure onto said substrate, said projection of said fourth conducting structure onto said substrate completely inside said projection of said second conducting structure onto said substrate; and said projection of said fourth conducting structure onto said substrate approximately parallel to said projection of said third conducting structure onto said substrate at least seven times longer than said side of said projection of said fourth conducting structure onto said substrate approximately parallel to said projection of said first conducting structure onto said substrate.
2. The transistor as set forth in claim 1 , wherein the side of said projection of said fourth conducting structure onto said substrate approximately parallel to said projection of said third conducting structure onto said substrate far longer than the side of said projection of said fourth conducting structure onto said substrate approximately parallel to said projection of said first conducting structure onto said substrate.
3. The transistor as set forth in claim 1 , further comprising a fifth conducting structure upon said substrate contacting with said fourth conducting structure, with the projection of said fifth conducting structure onto said substrate separated from said projection of said first and said third conducting structure onto said substrate, said projection of said fifth conducting structure onto said substrate at least partly inside said projection of said second conducting structure onto said substrate, said projection of said fifth and said third conducting structure onto said substrate on the opposite sides of said projection of said fourth conducting structure onto said substrate, and the side of said projection of said fourth conducting structure onto said substrate facing said projection of said fifth conducting structure onto said substrate only partly contacting with said projection of said fifth conducting structure onto said substrate.
4. The transistor as set forth in claim 3 , wherein the area of said projection of said fourth conducting structure onto said substrate far larger than that of the overlap between said projection of said fifth and said second conducting structure.
5. The transistor as set forth in claim 1 , further comprising a semiconductor layer upon said substrate electrically coupling with said third and said fourth conducting structure, with the projection of said semiconductor layer onto said substrate completely inside said projection of said second conducting structure onto said substrate.