High voltage semiconductor device having current localization region
A high voltage semiconductor device, having a first layer of semiconductor material, a current localization region, a second layer of semiconductor material and a third layer of semiconductor material, is utilized to improve the electrical characteristics of the device by reducing the thickness of the second layer. The reduction of the thickness of the second layer provides for a reduction in edge failures as compared to prior art. The reduced thickness of the second layer also provides for a reduction in forward voltage drop across the device. The reduced thickness of the second layer also results in a reduced dynamic impedance of the device.
1 . A semiconductor device comprising:
a first layer of semiconductor material of a first layer conductivity type, the first layer of semiconductor material having first and second sides;
a second layer of semiconductor material of a second layer conductivity type, the second layer of semiconductor material having first and second sides with the first side of the first layer adjacent the second side of the second layer; and
a current localization region positioned in the first layer of semiconductor material and in the second layer of semiconductor material and adjacent to the first side of the first layer of semiconductor material, the current localization region extending beyond the first side of the first layer of semiconductor material into the second layer.
2 . The semiconductor device as claimed in claim 1 wherein the first layer conductivity type and the second layer conductivity type are a same conductivity type.
3 . The semiconductor device as claimed in claim 2 wherein the same conductivity type is N type.
4 . The semiconductor device as claimed in claim 1 wherein the second layer of semiconductor varies in width, such that a central portion of the second layer of semiconductor is thinner than sides of the second layer of semiconductor.
5 . The semiconductor device as claimed in claim 1 wherein a distance in a central portion of the device from the current localization region to the third layer of semiconductor material is less than a distance from the first layer of semiconductor material to the third layer of semiconductor material at the edge of the device.
6 . The semiconductor device as claimed in claim 1 further including a third layer of semiconductor material of a third layer conductivity type, the third layer of semiconductor material having first and second sides, wherein the first side is adjacent the second side of the second layer of semiconductor material.
7 . The semiconductor device as claimed in claim 1 further including a first layer dopant and a current localization region dopant wherein the current localization region dopant diffuses faster than the first layer dopant.
8 . The semiconductor device as claimed in claim 7 wherein the first layer dopant comprises arsenic, and the current localization dopant comprises phosphorus.
9 . The semiconductor device as claimed in claim 7 wherein the first layer dopant comprises boron and Cesium (CS-135), and the current localization dopant comprises phosphorus.
10 . The semiconductor device as claimed in claim 1 wherein the current localization dopant is substantially the same as the first layer dopant.
11 . A method of fabricating a semiconductor device, the method comprising:
forming a low resistivity first layer of semiconductor material;
introducing a dopant into the low resistivity layer at a predetermined location;
forming a high resistivity second layer of semiconductor material; and
heating to diffuse the dopant to form a current localization region.
12 . The method of fabricating a semiconductor device as claimed in claim 11 wherein the dopant is phosphorus.
13 . The method of fabricating a semiconductor device as claimed in claim 11 wherein the first layer of semiconductor material is N+.
14 . The method of fabricating a semiconductor device as claimed in claim 11 wherein the second layer of semiconductor material is N−.
15 . The method of fabricating a semiconductor device as claimed in claim 11 wherein the third layer of semiconductor material is P+.
16 . The method of fabricating a semiconductor device as claimed in claim 11 wherein introducing a dopant is performed through ion implantation.
17 . The method of fabricating a semiconductor device as claimed in claim 11 further including forming a third layer of semiconductor material.
18 . A method of fabricating a semiconductor device, the method comprising:
forming a first layer of semiconductor material;
thereafter, introducing ions in the first layer of semiconductor material;
thereafter, forming a second layer of semiconductor material on the first layer; and
thereafter, heating the device to diffuse the implanted ions.
19 . The method of fabricating a semiconductor device as claimed in claim 18 further including, forming a third layer of semiconductor material.
20 . A method of fabricating a semiconductor device, the method comprising:
forming a low resistivity first layer of semiconductor material and having a first layer dopant;
introducing a current localization dopant into the low resistivity layer at a predetermined location, the current localization dopant having a faster diffusion rate than the first layer dopant;
forming a high resistivity second layer of semiconductor material; and
heating to diffuse the dopant to form a current localization region.