IP Library Granted Patent US 7,281,187
Granted Patent B2
US 7,281,187 · App. 10/720,016 · Granted Oct 9, 2007

Using error checking bits to communicated an address or other bits

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Quick Facts
Patent No.
US 7,281,187
App. No.
10/720,016
Granted
Oct 9, 2007
Kind
B2
Abstract

A method of operating in a network in which a plurality of stations communicate over a shared medium. The method comprises transmitting a group of bits from a transmitting station to a receiving station, wherein the group of bits comprises information bits and error checking bits, and communicating additional bits from the transmitting station to the receiving station without transmitting the additional bits. Communicating the additional bits comprises, at the transmitting station, deriving the error checking bits from the additional bits using an error checking process; and at the receiving station, using the same or a related error checking process to process candidate bits known to the receiving station, and comparing the output of the error checking process to the error checking bits received from the transmitting station to determine if the candidate bits correspond to the additional bits.

Claims (19)

1. A method of operating in a network in which a plurality of stations communicate over a shared medium, comprising

transmitting a group of bits from a transmitting station to a receiving station, wherein the group of bits comprises information bits and error checking bits;

communicating additional bits from the transmitting station to the receiving station without transmitting the additional bits, the communicating of the additional bits comprises

at the transmitting station, deriving the error checking bits from the additional bits using an error checking process; and

at the receiving station, using the same or a related error checking process to process candidate bits known to the receiving station, and comparing the output of the error checking process to the error checking bits received from the transmitting station to determine if the candidate bits correspond to the additional bits.

2. The method of claim 1 wherein the communicating of the additional bits further comprises

at the transmitting station, deriving the error checking bits from the additional bits and the information bits using the error checking process; and

at the receiving station, using the same or a related error checking process to process the candidate bits and the information bits received from the transmitting station, comparing the output of the error checking process result to the error checking bits received from the first station to determine if the candidate bits correspond to the additional bits.

3. The method of claim 1 wherein the additional bits comprise an address identifying one or both of the transmitting and receiving stations.

4. The method of claim 3 wherein the group of bits constitutes a packet, the information bits comprise a source address and data, and the additional bits comprise a destination address identifying the receiving station.

5. The method of claim 3 wherein the group of bits constitutes a packet, the information bits comprise a source address and data, and the additional bits comprise at least a portion of a destination address at least partially identifying the receiving station.

6. The method of claim 3 wherein the group of bits constitutes a Request To Send (RTS), the information bits comprise a source address and data, with the source address identifying the transmitting station, and the additional bits comprise a destination address identifying the receiving station.

7. The method of claim 3 wherein the group of bits constitutes a RTS, the information bits comprise a source address and data, with the source address identifying the transmitting station, and the additional bits comprise at least a portion of a destination address at least partially identifying the receiving station.

8. The method of claim 3 wherein the group of bits constitutes a Clear To Send (CTS) transmitted in response to an RTS, and the additional bits comprise one or both of the following: (1) a destination address identifying the receiving station and (2) a source address identifying the transmitting station.

9. The method of claim 3 wherein the group of bits constitutes an acknowledgement, and the additional bits comprise one or both of the following: (1) a source address identifying the transmitting station and (2) a destination address identifying the receiving station.

10. The method of claim 3 wherein the group of bits constitutes an acknowledgement and the additional bits comprise one or both of the following: (1) at least a portion of a source address at least partially identifying the transmitting station and (2) at least a portion of a destination address at least partially identifying the receiving station.

11. The method of claim 3 wherein the group of bits constitutes an acknowledgement transmitted in response to a receipt of a packet, and the additional bits comprise a set of bits from the packet that is sufficiently unique as to associate the acknowledgement with the packet.

12. The method of claim 6 wherein the information bits comprise bits indicating which portions of a previously transmitted packet need to be retransmitted.

13. The method of claim 1 wherein the error checking process comprises a cyclic redundancy check, and the error checking bits comprise frame check sequence (FCS) bits associated with the cyclic redundancy check.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2013
From: QUALCOMM ATHEROS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 029555/0769 →
MERGER Recorded Nov 30, 2011
From: ATHEROS COMMUNICATIONS, INC.
To: QUALCOMM ATHEROS, INC.
Reel/Frame 027301/0678 →
MERGER Recorded Mar 19, 2010
From: INTELLON CORPORATION
To: ATHEROS POWERLINE LLC
Reel/Frame 024103/0834 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2010
From: ATHEROS POWERLINE LLC
To: ATHEROS COMMUNICATIONS, INC.
Reel/Frame 024103/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2004
From: YONGE III, LAWRENCE W.; KATAR, SRINIVAS
To: INTELLON CORPORATION
Reel/Frame 015204/0263 →