A memory array layer for use in a 3D RRAM is formed, with peripheral circuitry, on a silicon substrate; layers of silicon oxide, bottom electrode material, silicon oxide, resistor material, silicon oxide, silicon nitride, silicon oxide, top electrode and covering oxide are deposited and formed. Multiple memory array layers may be formed on top of one another. The RRAM of the invention may be programmed in a single step or a two step programming process.
1. A memoly array layer for use in a 3D RRAM comprising, on a silicon substrate having peripheral circuitry thereon:
a first layer of silicon oxide, deposited and planarized;
a bottom electrode formed of a material taken from the group of materials consisting of Pt, PtRhO x , PtIrO x and TiN/Pt;
a second oxide layer having a thickness of at least 1.5× that of the thickness of the bottom electrode, deposited and planarized to a level where at the bottom electrode is exposed; a layer of memory resistor material;
a layer of Si 3 N 4 ;
a third oxide layer having a thickness of about 1.5× of that of the memory resistor material; CMPd to expose the memory resistor surface;
a top electrode formed of a material taken from the group of materials consisting of Pt, PtRhO x , PtIrO x and TiN/Pt; and
a covering oxide layer.
2. The memory array layer of claim 1 wherein said first layer of silicon oxide has a thickness of between about 100 nm to 1000 nm; wherein said memory resistor material has a thickness of between about 20 nm to 150 nm; said Si 3 N 4 layer has a thickness of between about 10 nm to 30 nm; and wherein said third oxide layer has a thickness of about 1.5× of that of the memory resistor material.
3. The memory array layer of claim 1 wherein said bottom electrode and said top electrode have, for an electrode taken from the group of electrodes formed of Pt, PtRhO x , PtIrO x , a thickness of between about 50 nm to 300 nm, or for a bi-layer TiN/Pt, a thickness of between about 10 nm to 200 nm of TiN and between about 10 nm to 100 nm of Pt.