Method of fabricating semiconductor integrated circuit device

1. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:

(a) forming an isolation groove in a silicon surface of a first major surface of a wafer, so as to divide the silicon surface into two regions which are to be first and second regions;

(b) forming a first insulating film of silicon oxide by chemical vapor deposition, the first insulating film covering the silicon surface;

(c) planarizing the silicon surface covered with the first insulating film by removing the first insulating film outside the isolation groove with chemical mechanical polishing:

(d) forming two gate electrodes, to be N- and P-type gate electrode respectively over the first and second regions, each of said two gate electrodes having a silicon film to be a polysilicon conductive film;

(e) forming N-type source and drain regions in the first region, said N-type source and drain regions to constitute a first insulated gate field effect transistor together with the N-type gate electrode and a pair of first insulating side walls;

(f) forming P-type source and drain regions in the second region, said P-type source and drain regions to constitute a second insulated gate field effect transistor together with the P-type gate electrode and a pair of second insulating side walls;

(g) exposing surface portions of the silicon surface over said N-type and P-type source regions and drain regions;

(h) depositing a Co film covering at least the exposed surface portions, by sputtering, from a Co sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, wherein a sum of Fe and Ni in the Co sputtering target is not greater than 50 ppm by weight, and wherein the sputtering is performed in such a manner that the composition of the deposited Co film is substantially the same as that of the Co sputtering target;

(i) performing first rapid thermal annealing at a first temperature to the first major surface formed with the Co film so as to form Co monosilicide films over the surface portions, leaving a remaining Co film not formed into Co monosilicide, wherein the first temperature is a temperature that creep-up across the first and second insulating side walls substantially does not take place;

(j) removing the remaining Co film, remaining over the first major surface, by wet etching; and

(k) after step (j), performing second rapid thermal annealing at a second temperature higher than the first temperature to the first major surface so as to form Co disilicide films over the surface portions.

2. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the first temperature is not higher than 525° C.

3. A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.

4. A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.

5. A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein the first temperature is not lower than 475° C.

6. A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein the semiconductor integrated circuit device is designed under design rules not larger than 0.25 μm.

7. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein the Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.

8. A method of fabricating a semiconductor integrated circuit device according to claim 7 , wherein the second temperature is from 650° to 800° C.

9. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein said P-type gate electrode is doped with boron.