IP Library Granted Patent US 7,302,461
Granted Patent B2
US 7,302,461 · App. 10/724,443 · Granted Nov 27, 2007

Analog delay elements

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Quick Facts
Patent No.
US 7,302,461
App. No.
10/724,443
Granted
Nov 27, 2007
Kind
B2
Abstract

Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response over a wide frequency range while being tolerant of process variations.

Claims (50)

1. A delay element comprising:

an amplifier adapted to receive input signals;

a filter coupled to the amplifier and adapted to provide a variable delay, wherein the filter comprises:

a first inductor having a first terminal and a second terminal, the first terminal coupled to a first output terminal of the amplifier and the second terminal providing a first output signal of the delay element;

a second inductor having a third terminal and a fourth terminal, the third terminal coupled to a second output terminal of the amplifier and the fourth terminal providing a second output signal of the delay element;

at least a first capacitor coupled between the first output terminal of the amplifier and the fourth terminal of the second inductor, wherein a capacitance of the at least first capacitor is variable; and

at least a second capacitor coupled between the second output terminal of the amplifier and the second terminal of the first inductor, wherein a capacitance of the at least second capacitor is variable.

2. The delay element of claim 1 , wherein the filter further comprises:

at least a third capacitor coupled between the fourth terminal of the second inductor and a reference terminal, wherein a capacitance of the at least third capacitor is variable; and

at least a fourth capacitor coupled between the second terminal of the first inductor and the reference terminal, wherein a capacitance of the at least fourth capacitor is variable.

3. The delay element of claim 2 , wherein the reference terminal is at a ground voltage potential.

4. The delay element of claim 2 , wherein the amplifier is a differential amplifier comprising:

a pair of transistors;

a pair of resistors coupled between a supply voltage and corresponding ones of the transistors; and

a current source coupled between the pair of transistors and the reference terminal.

5. The delay element of claim 2 , wherein the at least first and second capacitors each comprises:

a first fixed capacitor;

at least one selectable fifth capacitor coupled in parallel with the first fixed capacitor; and

a first transistor in series with each selectable fifth capacitor and adapted to be controlled to determine whether the associated selectable fifth capacitor is enabled.

6. The delay element of claim 5 , wherein the at least third and fourth capacitors each comprises:

a second fixed capacitor;

at least one selectable sixth capacitor coupled in parallel with the second fixed capacitor; and

a second transistor in series with each selectable sixth capacitor and adapted to be controlled to determine whether the associated selectable sixth capacitor is enabled.

7. The delay element of claim 2 , wherein the delay element is programmable for the variable delay and to account for semiconductor processing variations.

8. The delay element of claim 2 , wherein the filter is an allpass filter and the delay element is adapted to provide an approximately flat magnitude and group delay response across a frequency range.

9. The delay element of claim 1 , wherein the amplifier is a differential amplifier.

10. A method of providing a variable signal delay, the method comprising:

receiving an input signal;

amplifying the input signal to provide an amplified output signal;

passing the amplified output signal through a filter having inductors and cross-coupled capacitors whose capacitance is variable; and

providing an output signal across load capacitors of the filter whose capacitance is variable to provide a desired signal delay.

11. The method of claim 10 , wherein the capacitance of the cross-coupled capacitors is variable to account for semiconductor processing variations.

12. The method of claim 10 , wherein the filter is an allpass filter adapted to provide an approximately constant group delay and magnitude response over a frequency range.

13. A method of providing a signal delay, the method comprising:

providing an amplifier adapted to amplify input signals and provide amplified output signals; and

providing a filter adapted to filter the amplified output signals, the filter having cross-coupled capacitors and load capacitors whose capacitance is variable to provide a selectable signal delay.

14. The method of claim 13 , wherein the capacitance of the cross-coupled capacitors is variable to account for semiconductor processing variations.

15. The method of claim 13 , wherein the filter is an allpass filter adapted to provide an approximately flat magnitude and group delay response across a frequency range.

16. A delay element comprising:

an amplifier adapted to receive input signals and provide a first signal and a second signal;

a first and a second inductor in series, wherein the first inductor receives the first signal at a first terminal and the second inductor provides a first output signal at a second terminal;

a first capacitor coupled between the first and second inductor and a reference terminal;

a third and a fourth inductor in series, wherein the third inductor receives the second signal at a third terminal and the fourth inductor provides a second output signal at a fourth terminal;

a second capacitor coupled between the third and fourth inductor and the reference terminal;

a third capacitor coupled to the first terminal and the fourth terminal;

a fourth capacitor coupled to the third terminal and the second terminal;

a fifth capacitor coupled to the second terminal and the reference terminal; and

a sixth capacitor coupled to the fourth terminal and the reference terminal.

17. The delay element of claim 16 , wherein the third, fourth, fifth, and sixth capacitor are adapted to have a variable capacitance.

18. The delay element of claim 16 , wherein the third, fourth, fifth, and sixth capacitor each comprises a fixed capacitor in parallel with a selectively enabled capacitor.

Assignments (2)
CHANGE OF NAME Recorded May 29, 2014
From: SCINTERA NETWORKS, INC.
To: SCINTERA NETWORKS LLC
Reel/Frame 033047/0864 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2004
From: MUKHERJEE, DEBANJAN; BHATTACHARJEE, JISHNU; YU, QIAN; PHANSE, ABHIJIT
To: SCINTERA NETWORKS, INC.
Reel/Frame 015196/0350 →