Method for optimizing MRAM circuit performance
View Patent ↗A method to adjust an operating parameter of a magnetoresistive random access memory having a tunable circuit, such as a bias control circuit, provides for measuring the operating parameter, such as a word current or sense current, of the magnetoresistive random access memory to obtain a measured operating parameter result and tuning the tunable circuit, such as with trimmable resistors, based on the measured operating parameter result. A method is also provided to adjust an operating parameter of a wafer of magnetic random access memories each having a tunable circuit by measuring the operating parameter one or more of the magnetic random access memories to obtain a measured operating parameter result and tuning some or all of the tunable circuits based on the measured operating parameter result.
1. A bias tuning circuit for a MRAM comprising, in combination:
a bias generator having a bias output;
a plurality of switches, each of the switches having a word reference input and a mirror transistor output;
a plurality of mirror transistors connected to the mirror transistor outputs;
a transistor connected to the bias output of the bias generator and further connected in a mirror configuration with the plurality of mirror transistors and having a tuned reference output; and
a selector to select one of the mirror transistors to activate the transistor to set a voltage to the plurality of mirror transistors.
2. The bias tuning circuit of claim 1 with the each one of the plurality of mirror transistors having a different gain.
3. The bias tuning circuit of claim 1 further comprising, in combination:
a pad;
a indicator transistor in a mirror configuration with the transistor and connected to the pad to provide an indicator.
4. The bias tuning circuit of claim 3 with the pad being an external pad.
5. The bias tuning circuit of claim 3 with the indicator transistor having a gain that is a multiple of the transistor.
6. The bias tuning circuit of claim 1 with the plurality of mirror transistors are n-channel transistors.
7. The bias tuning circuit of claim 1 with the plurality of switches being transistors.
8. The bias tuning circuit of claim 1 with the transistor being an N-channel transistor.
9. The bias tuning circuit of claim 1 with the bias generator being a temperature and voltage compensated bias generator.
10. The bias turning circuit of claim 1 with the selector selecting one of the plurality of mirror transistors to compensate for a tested parameter.
11. The bias tuning circuit of claim 10 with the tested parameter being a manufacturing variance.