Fabrication method and structure of semiconductor non-volatile memory device
View Patent ↗A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
1. A non-volatile semiconductor memory device, comprising:
a semiconductor substrate;
first and second semiconductor regions of a first conductivity type formed in said semiconductor substrate;
a first channel region and a second channel region between said first semiconductor region and said second semiconductor region in said semiconductor substrate, said first channel region being located on the side close to said first semiconductor region and said second channel region being located on the side close to said second semiconductor region;
a first gate formed above said first channel region via a first insulator; and
a second gate formed above said second channel region via a second insulator,
wherein said non-volatile memory is enabled to perform at least a writing operation, an erasing operation and a charge holding operation, and such that in the writing operation electrons are injected into said second insulator, in the erasing operation holes are injected into said second insulator and in the holding operation charges are held in said second insulator, and
wherein the charge density of an impurity in said first channel region is different from the charge density of an impurity in said second channel region.
2. The non-volatile semiconductor memory device according to claim 1 ,
wherein the charge density of an impurity in said second channel region is lower than the charge density of an impurity in said first channel region.
3. The non-volatile semiconductor memory device according to claim 1 ,
wherein an impurity of a second conductivity type, opposite to said first conductivity type, is introduced into said first channel region, and the impurity of the first conductivity type and the impurity of the second conductivity type are introduced into said second channel region.
4. The non-volatile semiconductor memory device according to claim 1 ,
wherein said second insulator is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
5. The non-volatile semiconductor memory device according to claim 1 ,
wherein the thickness of said second insulator is larger than the thickness of said first insulator.
6. The non-volatile semiconductor memory device according to claim 1 ,
wherein the charge density of an impurity in said second channel region is set within the range of 10 17 /cm 3 to 10 18 /cm 3 .
7. The non-volatile semiconductor memory device according to claim 1 ,
wherein said second gate is adjacent to said first gate via said second insulator.
8. A non-volatile semiconductor memory device, comprising:
a semiconductor substrate;
first and second semiconductor regions of a first conductivity type formed in said semiconductor substrate;
a first channel region and a second channel region between said first semiconductor region and said second semiconductor region in said semiconductor substrate, said first channel region being located on the side close to said first semiconductor region and said second channel region being located on the side close to said second semiconductor region;
a first gate formed above said first channel region via a first insulator; and
a second gate formed above said second channel region via a second insulator,
wherein said non-volatile memory is enabled to perform at least a writing operation, an erasing operation and a charge holding operation, and such that in the writing operation electrons are injected into said second insulator and in the erasing operation holes are injected into said second insulator, in the erasing operation holes are injected into said second insulator and in the holding operation charges are held in said second insulator, and
wherein said second channel region includes a first region on the side close to said second semiconductor region and a second region on the side close to said first channel region, and the charge density of an impurity in said first region is higher than the charge density of an impurity in said second region.
9. The non-volatile semiconductor memory device according to claim 8 ,
wherein the impurity concentration of the second conductivity type, opposite to said first conductivity type, of said first region is higher than the impurity concentration of the second conductivity type of said second region.
10. The non-volatile semiconductor memory device according to claim 8 ,
wherein the impurity of the second conductivity type is introduced into said first channel region, the impurity of the first conductivity type and the impurity of the second conductivity type are introduced into said second channel region, and the impurity concentration of the second conductivity type of said first region is higher than the impurity concentration of the second conductivity type of said second region.
11. The non-volatile semiconductor memory device according to claim 10 ,
wherein said second insulator is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
12. The non-volatile semiconductor memory device according to claim 8 ,
wherein said second insulator is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
13. The non-volatile semiconductor memory device according to claim 8 ,
wherein the charge density of an impurity in said first channel region is higher than the charge density of an impurity in said second region.
14. The non-volatile semiconductor memory device according to claim 13 ,
wherein said second insulator is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
15. The non-volatile semiconductor memory device according to claim 8 ,
wherein said second gate is adjacent to said first gate via said second insulator.
16. The non-volatile semiconductor memory device according to claim 15 ,
wherein said second insulator is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.