Data rate equalisation to account for relatively different printhead widths
View Patent ↗A printer controller configured to generate dot data for supply to a printhead that includes at least first and second longitudinally extending printhead chips that are positioned adjacent each other either side of a join region such that a printing width of the printhead is wider than the length of either printhead chip, the printer controller being configured such that, in the event that the printhead chips to which dot data is being supplied are of sufficiently unequal relative length, the dot data is supplied more frequently, or at a higher rate, to the longer of the two printhead chips.
1. A printer controller configured to generate dot data for supply to a printhead that includes at least first and second longitudinally extending printhead chips that are positioned adjacent each other either side of a join region such that a printing width of the printhead is wider than the length of either printhead chip, the printer controller being configured such that, in the event that the printhead chips to which dot data is being supplied are of sufficiently unequal relative length, the dot data is supplied more frequently, or at a higher rate, to the longer of the two printhead chips.
2. A printer controller according to claim 1 , configured to supply the dot data to the printhead modules such that none of the printhead modules is full and ready for printing substantially earlier than any of the other printhead modules.
3. A printer controller according to claim 1 , wherein the dot data is supplied to the printhead from a memory under the control of the printhead controller.
4. A printer controller according to claim 1 , including a hardware module for undertaking the task of bandwidth management.
5. A printer controller according to claim 4 , wherein the hardware module is also configured to compensate for different length printheads.
6. A printer controller according to claim 1 , configured to manipulate the supply of dot data to each of the printhead modules such that memory bandwidth usage is substantially constant during a printhead loading cycle.