IP Library Granted Patent US 7,277,687
Granted Patent B2
US 7,277,687 · App. 10/727,263 · Granted Oct 2, 2007

Low power amplitude modulation detector

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Quick Facts
Patent No.
US 7,277,687
App. No.
10/727,263
Granted
Oct 2, 2007
Kind
B2
Abstract

An AM demodulator using totem pole complementary metal oxide semiconductor transistors having a feedback to provide a common gate voltage of approximately half that across the transistors in the totem pole. The AM demodulator used in a hearing assistance device and in a programmer of a hearing assistance device.

Claims (37)

1. An apparatus comprising:

a p-channel metal oxide semiconductor (PMOS) transistor having a first drain and further having a first source connected to a first load at an output node, the first load having another connection to a first voltage reference; and

an n-channel metal oxide semiconductor (NMOS) transistor having a second drain connected to the first drain of the PMOS transistor at a feedback node, the NMOS transistor having a second source connected to a second load, the second load having another connection to a second voltage reference,

wherein the first gate of the PMOS transistor and the second gate of the NMOS transistor are connected to a coupling capacitor, the coupling capacitor receiving radio frequency input signals and wherein the first gate and second gate receive a feedback from the feedback node.

2. The apparatus of claim 1 , wherein the first load is a resistor.

3. The apparatus of claim 1 , wherein the first load is a transistor.

4. The apparatus of claim 1 , wherein the second load is a resistor.

5. The apparatus of claim 1 wherein the second load is a transistor.

6. The apparatus of claim 1 , wherein the feedback comprises a signal passing through a third load.

7. The apparatus of claim 6 , wherein the third load is a resistor.

8. The apparatus of claim 6 , wherein the third load is a transistor.

9. The apparatus of claim 1 , wherein the PMOS transistor and NMOS transistor are complementary metal oxide semiconductor (CMOS) transistors.

10. The apparatus of claim 1 , wherein the first voltage reference is a positive supply voltage and the second voltage reference is a ground.

11. The apparatus of claim 1 , wherein: the PMOS transistor and NMOS transistor are complementary metal oxide semiconductor (CMOS) transistors; the feedback includes a third load; the first load, second load, and third load are resistor-connected transistors; and the PMOS transistor, NMOS transistor, first load, second load, and third load are fabricated in an integrated circuit.

12. The apparatus of claim 11 , wherein the first voltage reference is a positive supply voltage and the second voltage reference is a ground.

13. An apparatus, comprising:

a microphone connected to a controller;

a receiver connected to the controller; and

an antenna connected to communication electronics, the communication electronics connected to the controller and comprising:

a p-channel metal oxide semiconductor (PMOS) transistor having a first drain and further having a first source connected to a first load at an output node, the first load having another connection to a first voltage reference; and

an n-channel metal oxide semiconductor (NMOS) transistor having a second drain connected to the first drain of the PMOS transistor at a feedback node, the NMOS transistor having a second source connected to a second load, the second load having another connection to a second voltage reference,

wherein the first gate of the PMOS transistor and the second gate of the NMOS transistor are connected to a coupling capacitor, the coupling capacitor receiving radio frequency input signals and wherein the first gate and second gate receive a feedback from the feedback node.

14. The apparatus of claim 13 , wherein: the PMOS transistor and NMOS transistor are complementary metal oxide semiconductor (CMOS) transistors; the feedback includes a third load; the first load, second load, and third load are resistor-connected transistors; and the PMOS transistor, NMOS transistor, first load, second load, and third load are fabricated in an integrated circuit.

15. The apparatus of claim 14 , wherein the first voltage reference is a positive supply voltage and the second voltage reference is a ground.

16. An apparatus, comprising:

a memory connected to a controller;

an input device connected to the controller; and

an antenna connected to communication electronics, the communication electronics connected to the controller and comprising:

a p-channel metal oxide semiconductor (PMOS) transistor having a first drain and further having a first source connected to a first load at an output node, the first load having another connection to a first voltage reference; and

an n-channel metal oxide semiconductor (NMOS) transistor having a second drain connected to the first drain of the PMOS transistor at a feedback node, the NMOS transistor having a second source connected to a second load, the second load having another connection to a second voltage reference,

wherein the first gate of the PMOS transistor and the second gate of the NMOS transistor are connected to a coupling capacitor, the coupling capacitor receiving radio frequency input signals and wherein the first gate and second gate receive a feedback from the feedback node.

17. The apparatus of claim 16 , wherein: the PMOS transistor and NMOS transistor are complementary metal oxide semiconductor (CMOS) transistors; the feedback includes a third load; the first load, second load, and third load are resistor-connected transistors; and the PMOS transistor, NMOS transistor, first load, second load, and third load are fabricated in an integrated circuit.

18. The apparatus of claim 17 , wherein the first voltage reference is a positive supply voltage and the second voltage reference is a ground.

19. A method, comprising:

receiving an amplitude modulated signal; and

processing the amplitude modulated signal with a capacitively coupled demodulator comprising a totem pole configuration of complementary metal oxide semiconductor transistors including providing a feedback signal to a gate of each of the complementary metal oxide semiconductor transistors to generate a demodulated signal.

20. The method of claim 19 , wherein the step of receiving comprises filtering the amplitude modulated signal.

Assignments (1)
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Aug 25, 2018
From: STARKEY LABORATORIES, INC.
To: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046944/0689 →