Semiconductor device
View Patent ↗A semiconductor device of the present invention has two inner inner leads to be bonded with inner-side bump electrodes each placed at a position which is a relatively large distance apart from the edge of a semiconductor chip, between outer-side bump electrodes each placed at a position which is a relatively small distance apart from the edge of the semiconductor chip. At least one of the inner inner leads is bent in accordance with a bonding position with the inner-side bump electrode.
1. A semiconductor device including a semiconductor chip, comprising:
edge-side bump electrodes each placed on the semiconductor chip at a position which is a relatively small distance apart from an edge of the semiconductor chip; and
inside bump electrodes each placed on the semiconductor chip at a position which is a relatively large distance apart from the edge of the semiconductor chip,
the edge-side bump electrodes and the inside bump electrodes being bonded with lead wires provided on a film substrate,
wherein:
between the edge-side bump electrodes adjacent to each other provided are at least two lead wires for inside bump electrode use which are bonded with the inside bump electrodes, and
at least one of the lead wires for inside bump electrode use is bent in accordance with a bonding position with the inside bump electrode.
2. The semiconductor device according to claim 1 , wherein:
the lead wires for inside bump electrode use are provided so as to be at a smaller pitch between the edge-side bump electrodes than at the bonding positions with the inside bump electrodes.
3. The semiconductor device according to claim 2 , wherein:
the lead wire for inside bump electrode use is bent between a position where the edge-side bump electrode is placed and a position where the inside bump electrode is placed.
4. The semiconductor device according to claim 1 , wherein:
the lead wire for inside bump electrode use between the edge-side bump electrodes has a width of not less than 1 μm nor more than 15 μm.
5. The semiconductor device according to claim 1 , wherein:
a distance between the edge-side bump electrodes is not less than 50 μm nor more than 150 μm.
6. The semiconductor device according to claim 1 , wherein:
when bonded with the inside bump electrode, the lead wire for inside bump electrode use is not less than 100 μm nor more than 500 μm in length, extending from the edge of the semiconductor chip to an inside end of the inside bump electrode.
7. The semiconductor device according to claim 1 , wherein:
the edge-side bump electrode and the inside bump electrode are provided in a periphery along at least one of four edges of the semiconductor chip, and
the inside bump electrode is larger in number than the edge-side bump electrode.
8. The semiconductor device according to claim 7 , wherein:
the inside bump electrodes placed at both ends among the inside bump electrodes are placed at positions on the inward side of the edge-side bump electrodes placed at both ends among the edge-side bump electrodes in a direction parallel to the edge of the semiconductor chip.
9. The semiconductor device according to claim 1 , wherein:
at least some of the inside bump electrodes are placed in a direction different from a direction in which the edge-side bump electrode is placed.
10. The semiconductor device according to claim 9 , wherein:
among the inside bump electrodes, the inside bump electrodes having a direction different from a direction in which the edge-side bump electrode is placed are placed at positions which are a relatively larger distance apart from the edge of the semiconductor chip than other inside bump electrodes.
11. The semiconductor device according to claim 9 , wherein:
at least some of the inside bump electrodes are connected to at least one of a semiconductor element and a chip interconnection on the semiconductor chip.
12. The semiconductor device according to claim 1 , wherein:
the number of the lead wires for inside bump electrode use which are provided between the edge-side bump electrodes placed at least at both ends and their adjacent positions among the edge-side bump electrodes may be less than the number of the lead wires for inside bump electrode use which are provided between the edge-side bump electrodes placed at positions other than the both ends.
13. The semiconductor device according to claim 12 , wherein:
respective widths of the edge-side bump electrodes and the inside bump electrodes placed at least at both ends among the edge-side bump electrodes and the inside bump electrodes may be larger than respective widths of the edge-side bump electrodes and the inside bump electrodes placed at positions other than the both ends.
14. The semiconductor device according to claim 1 , wherein:
the inside bump electrode further includes first inside bump electrodes each placed at a position which is a relatively small distance apart from the edge of the semiconductor chip and second inside bump electrodes each placed at a position which is a relatively large distance apart from the edge of the semiconductor chip, and
lead wires for inside bump electrode use which are bonded with the second inside bump electrodes are provided between at least some of the first inside bump electrodes which are adjacent to each other.
15. The semiconductor device according to claim 14 , wherein:
an electrode-to-electrode region where the lead wire for inside bump electrode use is provided and an electrode-to-electrode region where the lead wire for inside bump electrode use is not provided are alternately provided between the first inside bump electrodes adjacent to each other.