Low voltage signal stripping circuit for an RFID reader
View Patent ↗A reader of an RFID system has excitation circuitry for generating a higher voltage excitation signal, receiving circuitry for reading a lower voltage transponder signal and an antenna coupled with the excitation circuitry for transmitting the excitation signal and coupled with the receiving circuitry for receiving the transponder signal. The receiving circuitry includes a low voltage signal stripping circuit coupled with the antenna for isolating the transponder signal from the excitation signal preliminary to the receiving circuitry reading the transponder signal. The bulk of the components of the low voltage signal stripping circuit are low voltage components, which can be included in an application specific integrated circuit.
1. A reader of an RFID system comprising:
excitation circuitry for generating a higher voltage excitation signal;
receiving circuitry for reading a lower voltage transponder signal;
an antenna coupled with said excitation circuitry for transmitting said excitation signal and coupled with said receiving circuitry for receiving said transponder signal; and
a low voltage signal stripping circuit included in said receiving circuitry coupled with said antenna for isolating said transponder signal from said excitation signal preliminary to said receiving circuitry reading said transponder signal, said low voltage signal stripping circuit comprising an inlet resistor, an amplifier, a feedback circuit and a DC shift voltage or a DC shift current source, wherein said feedback circuit has a first pathway including a first pair of clamping diodes aligned in series in a first direction, a second pathway including a second pair of clamping diodes aligned in series in a second direction opposite said first direction, and a third pathway including a feedback resistor having a resistance.
2. The reader of claim 1 , wherein said inlet resistor is positioned in series between said antenna and said amplifier.
3. The reader of claim 1 , wherein said inlet resistor has a resistance about equal to said resistance of said feedback resistor.
4. The reader of claim 1 , wherein said amplifier and said feedback circuit are included in an application specific integrated circuit.
5. The reader of claim 1 , wherein said amplifier has a first input coupled with said inlet resistor and a second input tied to a reference voltage.
6. The reader of claim 5 , wherein said first input of said amplifier is an inverting negative input.
7. The reader of claim 5 , wherein said second input of said amplifier is a non-inverting positive input.
8. A reader of an RFID system comprising:
excitation circuitry for generating a higher voltage excitation signal;
receiving circuitry for reading a lower voltage transponder signal;
an antenna coupled with said excitation circuitry for transmitting said excitation signal and coupled with said receiving circuitry for receiving said transponder signal; and
a low voltage signal strinping circuit included in said receiving circuitry coupled with said antenna for isolating said transponder signal from said excitation signal preliminary to said receiving circuitry reading said transponder signal, said low voltage signal stripping circuit comprising an inlet resistor, an amplifier, a feedback circuit and a DC shift voltage or a DC shift current source, wherein said inlet resistor is a high voltage component and said amplifier and said feedback circuit are low voltage components.
9. The reader of claim 8 , wherein said feedback circuit has a pathway including a pair of clamping diodes aligned in series.
10. The reader of claim 8 , wherein said feedback circuit has a pathway including a feedback resistor having a resistance.
11. The reader of claim 10 , wherein said inlet resistor has a resistance about equal to said resistance of said feedback resistor.
12. The reader of claim 8 , wherein said inlet resistor is positioned in series between said antenna and said amplifier.
13. The reader of claim 8 , wherein said feedback circuit has a first pathway including a first pair of clamping diodes aligned in series in a first direction, a second pathway including a second pair of clamping diodes aligned in series in a second direction opposite said first direction, and a third pathway including a feedback resistor.
14. The reader of claim 8 , wherein said amplifier and said feedback circuit are included in an application specific integrated circuit.
15. The reader of claim 8 , wherein said amplifier has a first input coupled with said inlet resistor and a second input tied to a reference voltage.
16. The reader of claim 15 , wherein said first input of said amplifier is an inverting negative input.
17. The reader of claim 15 , wherein said second input of said amplifier is a non-inverting positive input.
18. A reader of an RFID system comprising:
excitation circuitry for generating a higher voltage excitation signal;
receiving circuitry for reading a lower voltage transponder signal;
an antenna coupled with said excitation circuitry for transmitting said excitation signal and coupled with said receiving circuitry for receiving said transponder signal;
a low voltage signal stripping circuit included in said receiving circuitry coupled with said antenna for isolating said transponder signal from said excitation signal preliminary to said receiving circuitry reading said transponder signal, said low voltage signal stripping circuit comprising an inlet resistor, an amplifier, a feedback circuit and a DC shift voltage or a DC shift current source; and
a summing node positioned upstream of said amplifier and downstream of said inlet resistor, said feedback circuit and said DC shift voltage or said DC shift current source to sum outputs from said inlet resistor, said feedback circuit and said DC shift voltage or said DC shift current source.
19. The reader of claim 18 , wherein said amplifier and said feedback circuit are included in an application specific integrated circuit.
20. The reader of claim 18 , wherein said inlet resistor is positioned in series between said antenna and said amplifier.
21. The reader of claim 18 , wherein said feedback circuit has a pathway including a pair of clamping diodes aligned in series.
22. The reader of claim 18 , wherein said feedback circuit has a pathway including a feedback resistor having a resistance.
23. The reader of claim 22 , wherein said inlet resistor has a resistance about equal to said resistance of said feedback resistor.
24. The reader of claim 18 , wherein said feedback circuit has a first pathway including a first pair of clamping diodes aligned in series in a first direction, a second pathway including a second pair of clamping diodes aligned in series in a second direction opposite said first direction, and a third pathway including a feedback resistor.
25. The reader of claim 18 , wherein said amplifier has a first input coupled with said inlet resistor and a second input tied to a reference voltage.
26. The reader of claim 25 , wherein said first input of said amplifier is an inverting negative input.
27. The reader of claim 25 , wherein said second input of said amplifier is a non-inverting positive input.
28. A reader of an RFID system comprising:
excitation circuitry for generating a higher voltage excitation signal;
receiving circuitry for reading a lower voltage transponder signal;
an antenna coupled with said excitation circuitry for transmitting said excitation signal and coupled with said receiving circuitry for receiving said transponder signal;
a low voltage signal stripping circuit included in said receiving circuitry coupled with said antenna for isolating said transponder signal from said excitation signal preliminary to said receiving circuitry reading said transponder signal, said low voltage signal stripping circuit comprising an inlet resistor, an amplifier, a feedback circuit and a DC shift voltage or a DC shift current source; and
a summing node positioned upstream of said amplifier and downstream of said inlet resistor, said feedback circuit and said DC shift voltage or said DC shift current source to sum outputs from said inlet resistor, said feedback circuit and said DC shift voltage or said DC shift current source, wherein said amplifier has a first input coupled with said summing node and a second input tied to a reference voltage.
29. The reader of claim 28 , wherein said first input of said amplifier is an inverting negative input.
30. The reader of claim 28 , wherein said second input of said amplifier is a non-inverting positive input.
31. The reader of claim 28 , wherein said amplifier and said feedback circuit are included in an application specific integrated circuit.
32. The reader of claim 28 , wherein said inlet resistor is positioned in series between said antenna and said amplifier.
33. The reader of claim 28 , wherein said feedback circuit has a pathway including a pair of clamping diodes aligned in series.
34. The reader of claim 28 , wherein said feedback circuit has a pathway including a feedback resistor having a resistance.
35. The reader of claim 34 , wherein said inlet resistor has a resistance about equal to said resistance of said feedback resistor.
36. The reader of claim 28 , wherein said feedback circuit has a first pathway including a first pair of clamping diodes aligned in series in a first direction, a second pathway including a second pair of clamping diodes aligned in series in a second direction opposite said first direction, and a third pathway including a feedback resistor.