Memory circuitry and method of forming memory circuitry
View Patent ↗A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors is received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.
1. Dynamic random access memory circuitry comprising:
a semiconductor substrate;
word lines received over the semiconductor substrate;
an insulative layer received over the word lines and the substrate, the insulative layer having at least a single well formed therein, the well comprising a base of said insulative layer received directly over the word lines, the insulative layer within which said well is formed peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area, said insulative layer of the well having a substantially planar base;
a plurality of memory cell storage capacitors received within said single well, the memory cell storage capacitors respectively comprising a storage node, the storage node comprising a portion having a container shape, said container-shaped portion of the storage node being received partially within the insulative layer through the insulative layer base of the well; and
peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array.
2. The memory circuitry of claim 1 wherein the insulative layer has a substantially planar outermost surface, and the capacitors have capacitor storage node electrodes having topmost surfaces received elevationally proximate the substantially planar outermost surface of the insulative layer.
3. The memory circuitry of claim 1 wherein the insulative layer is formed to have a substantially planar outermost surface, and the capacitors have capacitor storage node electrodes having topmost surfaces received elevationally above the substantially planar outermost surface of the insulative layer by less than 50 Angstroms.
4. The memory circuitry of claim 1 comprising buried digit lines; the well base having a lowest portion which is received at least 1000 Angstroms above outermost tops of the digit lines.
5. The memory circuitry of claim 1 wherein the oxygen diffusion barrier layer received over the well base comprises Si 3 N 4 .
6. The memory circuitry of claim 5 wherein the Si 3 N 4 -comprising layer has a thickness of from about 40 Angstroms to about 125 Angstroms.
7. The memory circuitry of claim 5 wherein the Si 3 N 4 -comprising layer has a thickness of from about 50 Angstroms to about 70 Angstroms.
8. The memory circuitry of claim 5 wherein the insulative layer comprises SiO 2 .
9. The memory circuitry of claim 8 wherein the Si 3 N 4 -comprising layer has a thickness of from about 40 Angstroms to about 125 Angstroms.
10. The memory circuitry of claim 8 wherein the Si 3 N 4 -comprising layer has a thickness of from about 50 Angstroms to about 70 Angstroms.
11. The memory circuitry of claim 1 wherein one of the storage node electrodes is spaced laterally inward of the outline peripherally defined by the well thereby forming a space between said one electrode and said outline.
12. Dynamic random access memory circuitry comprising:
a semiconductor substrate;
word lines received over the semiconductor substrate;
digit lines received over the word lines;
an insulative layer received over the word lines, the digit lines and the substrate, the insulative layer having at least a single well formed therein, the well comprising a base of said insulative layer received over the word lines and the digit lines, the insulative layer within which said well is formed peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area, an oxygen diffusion barrier layer received directly over the insulative layer base of the well;
a plurality of memory cell storage capacitors received within said single well over the word lines and the digit lines, the memory cell storage capacitors respectively comprising a storage node which is received within the insulative layer through the oxygen diffusion barrier layer and through the insulative layer base of the well; and
peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array.
13. The memory circuitry of claim 12 wherein the insulative layer has a substantially planar outermost surface, and the capacitors have capacitor storage node electrodes having topmost surfaces received elevationally proximate the substantially planar outermost surface of the insulative layer.
14. The memory circuitry of claim 12 wherein the insulative layer is formed to have a substantially planar outermost surface, and the capacitors have capacitor storage node electrodes having topmost surfaces received elevationally above the substantially planar outermost surface of the insulative layer by less than 50 Angstroms.
15. The memory circuitry of claim 12 wherein the one of the storage node electrode is spaced laterally inward of the outline peripherally defined by the well thereby forming a space between said one electrode and said outline.
16. The memory circuitry of claim 12 wherein the base is substantially planar.
17. The memory circuitry of claim 12 wherein the insulative layer is formed to have a substantially planar outermost surface, the memory cell storage capacitors respectively comprising an outer cell electrode having a topmost surface which is received elevationally outward of the insulative layer.
18. The memory circuitry of claim 12 wherein the Si 3 N 4 -comprising oxygen diffusion barrier layer is received on the well base.
19. The memory circuitry of claim 12 wherein the storage node comprises a portion having a container shape, said container-shaped portion being received partially within the insulative layer through the insulative layer base of the well.