Managing bursts of data
View Patent ↗Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first memory address has a first alignment with respect to the burst boundaries. The data is stored in the machine readable memory device a second time at a second memory address. The second memory address has a second alignment with respect to the burst boundaries.
1. A method for managing bursts of data, the method comprising:
storing data in a machine readable memory device a first time at a first memory address;
the machine readable memory device having two or more burst boundaries; and
the first memory address having a first alignment with respect to the burst boundaries;
storing the data in the machine readable memory device a second time at a second memory address, the second memory address having a second alignment with respect to the burst boundaries, the second alignment offset from the first alignment relative to the burst boundaries, the offset sufficient to enable selection for retrieval of the data from the first alignment or the second alignment; and
decoding a frame with a video decoder using at least a portion of the data, wherein the data represents at least one reference frame.
2. The method of claim 1 wherein the video decoder is an H.264 codec.
3. The method of claim 1 wherein the machine readable memory device comprises volatile memory.
4. The method of claim 3 wherein the volatile memory is one of static random access memory and dynamic random access memory.
5. The method of claim 1 wherein the machine readable memory device comprises non-volatile memory.
6. The method of claim 5 wherein the non-volatile memory is read-only memory.
7. The method of claim 1 further comprising storing the data in the machine readable memory device a third time at a third memory address, the third memory address having a third alignment with respect to the burst boundaries.
8. The method of claim 7 , further comprising:
outputting the decoded frame.
9. The method of claim 8 , wherein outputting the decoded frame comprises displaying the decoded frame.
10. The method of claim 1 , further comprising:
outputting the decoded frame.
11. The method of claim 10 , wherein outputting the decoded frame comprises displaying the decoded frame.
12. A method for use in managing bursts of data, the method comprising:
determining a set of desired bytes of data, the set of desired bytes of data having been previously stored in a machine readable memory device at two or more memory addresses, the memory device having at least two burst boundaries, and each memory address offset from the other memory address relative to the burst boundaries, the offset sufficient to enable selection for retrieval of the data from only one of the memory addresses; and
retrieving the desired bytes of data from a preferred memory address, the preferred memory address being aligned with the at least one burst boundary such that the number of bursts necessary to read the desired bytes from the preferred memory address is fewer than the number of bursts necessary to read the desired bytes from the other memory addresses; and
decoding a frame with a video decoder using at least a portion of the data, wherein the data represents at least one reference frame.
13. The method of claim 12 wherein the video decoder is an h.264 codec.
14. The method of claim 12 wherein the machine readable memory device comprises volatile memory.
15. The method of claim 14 wherein the volatile memory is one of static random access memory and dynamic random access memory.
16. The method of claim 12 wherein the machine readable memory device comprises non-volatile memory.
17. The method of claim 16 wherein the non-volatile memory is read-only memory.
18. A circuit for decoding video data, the circuit comprising:
a machine readable memory device, having two or more burst boundaries, for storing data starting at a first memory address that has a first alignment with respect to the burst boundaries, and concurrently storing the data starting at a second memory address that has a second alignment with respect to the burst boundaries, the second alignment offset from the first alignment relative to the burst boundaries, the offset sufficient to enable selection for retrieval of the data from the first alignment or the second alignment; and
a circuit for writing the data to the machine readable memory device a first time starting at the first memory address that has the first alignment with respect to the burst boundaries and writing the data in the machine readable memory device a second time starting at the second memory address that has the second alignment with respect to the burst boundaries; and
a video decoder for decoding a frame at least a portion of the data, wherein the data represents at least one reference frame.
19. The circuit of claim 18 , further comprising:
outputting the decoded frame.
20. The circuit of claim 19 , wherein outputting the decoded frame comprises displaying the decoded frame.
21. A circuit for decoding video data, said circuit comprising:
a machine readable memory device, having two or more burst boundaries, for storing data starting at a first memory address that has a first alignment with respect to burst boundaries, and concurrently storing the data starting at a second memory address that has a second alignment with respect to the burst boundaries, the second alignment offset from the first alignment relative to the burst boundaries, the offset sufficient to enable selection for retrieval of the data from the first alignment or the second alignment; and
a circuit for determining a first number of bursts for retrieving the data from the first address and determining a second number of bursts for retrieving the data from the second address and retrieving the data from the first address if the first number of bursts is fewer than the second number, and retrieving the data from the second address if the second number of bursts is fewer than the first number; and
a video decoder for decoding a frame at least a portion of the data, wherein the data represents at least one reference frame.
22. The circuit of claim 21 , further comprising:
outputting the decoded frame.
23. The circuit of claim 22 , wherein outputting the decoded frame comprises displaying the decoded frame.