IP Library Granted Patent US 6,888,745
Granted Patent B2
US 6,888,745 · App. 10/730,190 · Granted May 3, 2005

Nonvolatile memory device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,888,745
App. No.
10/730,190
Granted
May 3, 2005
Kind
B2
Abstract

An object of the present invention is to provide a mass-storage nonvolatile memory device capable of performing high speed operation. The nonvolatile memory device comprises a memory array comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising a variable resistor element formed of a manganese-containing oxide having a perovskite structure in which an electric resistance is varied by application of a voltage pulse and a variation amount of the electric resistance is variable depending on the magnitude of the voltage amplitude; and a program pulse generation circuit that, in order to program 3-level or larger multi-level data corresponding to one erase state and two or more program states into the variable resistor element, is capable of performing generation of program pulses having two or more different voltage amplitudes corresponding to the program states, the generation being separately performed corresponding to program data.

Claims (15)

1. A nonvolatile memory device comprising:

a memory array comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising a variable resistor element formed of a manganese-containing oxide having a perovskite structure in which an electric resistance is varied by application of a voltage pulse and a variation amount of the electric resistance is variable depending on the magnitude of the voltage amplitude; and

a program pulse generation circuit that, in order to program 3-level or larger multi-level data corresponding to one erase state and two or more program states into the variable resistor element, is capable of performing generation of program pulses having two or more different voltage amplitudes corresponding to the program states, the generation being separately performed corresponding to program data.

2. The nonvolatile memory device according to claim 1 , wherein:

the variable resistor element has voltage-resistance characteristics that monotonically increase or decrease the electric resistance when the voltage amplitude is increased in a state where the voltage amplitude is lower than or equal to a predetermined voltage;

when the program pulse is applied to the variable resistor element in the erase state, the voltage amplitude of the program pulse is higher than or equal to a program identification limit voltage provided in the form of a minimum value of a voltage amplitude sufficient to permit a resistance value to vary from a first resistance value in the erase state to exceed a variation range of the first resistance value.

3. The nonvolatile memory device according to claim 1 , wherein:

the variable resistor element has voltage-resistance characteristics in which in a state where the voltage amplitude is lower than or equal to a predetermined voltage, when the voltage amplitude is increased, the electric resistance monotonically increases or decrease, and a maximum resistance variation voltage exists at which a small increase or decrease amount of the electric resistance to a small increase in the voltage amplitude becomes maximum; and

of the two or more different voltage amplitudes of the program pulses, at least one voltage amplitude is lower than or equal to the maximum resistance variation voltage and at least one other voltage amplitude is higher than or equal to the maximum resistance variation voltage.

4. A nonvolatile memory device comprising:

a memory array comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising a variable resistor element formed of a manganese-containing oxide having a perovskite structure in which an electric resistance is varied by application of a voltage pulse and a variation amount of the electric resistance is variable depending on the magnitude of the voltage amplitude; and

a program pulse generation circuit that, in order to program binary data corresponding to one erase state and one program state into the variable resistor element, is capable of performing generation of program pulses having two or more different voltage amplitudes corresponding to the program states, the generation being separately performed corresponding to program data,

wherein:

the variable resistor element has voltage-resistance characteristics that monotonically increase or decrease the electric resistance when the voltage amplitude is increased in a state where the voltage amplitude is lower than or equal to a predetermined voltage; and

when the program pulse is applied to the variable resistor element in the erase state, the voltage amplitude of the program pulse is higher than or equal to a program identification limit voltage provided in the form of a minimum value of a voltage amplitude sufficient to permit a resistance value to vary from a first resistance value in the erase state to exceed a variation range of the first resistance value.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: INTELLECTUAL PROPERTIES I KFT.
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 029632/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2013
From: SHARP KABUSHIKI KAISHA
To: INTELLECTUAL PROPERTIES I KFT.
Reel/Frame 029574/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2003
From: EHIRO, MASAYUKI; INOUE, KOJI; AWAYA, NOBUYOSHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 014793/0482 →