Method and system for dynamically reducing length of a delay chain
View Patent ↗Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.
1. A method of reducing data path latency in digitally processing a sequence of data samples, the data path latency being associated with a transient processing operation on the data samples, comprising:
at the transition into the transient processing operation on the data samples reading the sequence of data samples into a tapped clocked delay chain, wherein each data storing element of the chain has an associated enabling signal for controlling, on any given clock cycle, whether to update or not its respective stored data sample;
during the transient processing operation on the data samples, processing data samples from taps on the clocked delay chain;
in response to receiving a signal of completion of the transient processing operation on the data samples, controlling the enabling signal of each data storing element in the chain to allow shifting data samples through an end portion of the clocked delay chain on a selected first set of clock cycles determining a first shifting rate and shifting data samples in an initial portion of the delay chain on a selected second set of clock cycles determining a second shifting rate, wherein the initial portion is complementary to the end portion and wherein the first shifting rate is higher than the second shifting rate; and
dynamically reducing the length of the clocked delay chain by moving the output of the delay chain to the last data storing element of the initial portion, after a number of clock cycles.
2. The method of claim 1 wherein the data samples are from a data packet.
3. The method of claim 2 wherein the data packet conforms to a transmission system selected from the group of 802.11a, 802.11g and HIPERLAN/2 transmission systems.
4. The method of claim 3 wherein the transient processing operation includes a synchronization of the data packet.
5. The method of claim 4 wherein the clocked delay chain comprises a plurality of pipelined registers.
6. The method of claim 5 wherein the reducing the length of the clocked delay chain is performed until a desired length of the clocked delay chain is achieved.
7. The method of claim 5 wherein reducing the length of the clocked delay chain further includes bypassing empty registers.
8. A method of reducing data path latency in digitally processing a sequence of data samples of a data packet, the data path latency being associated with synchronization of the data packet, comprising:
upon reception of the data packet, reading the sequence of data samples from the data packet into a tapped clocked delay chain comprising a plurality of pipelined registers, wherein each register has an associated enabling signal for controlling, on any given clock cycle, whether to update or not its respective stored data sample;
processing data samples from taps on the clocked delay chain to synchronize the data packet;
in response to receiving a signal of completion of synchronization of the data packet, controlling the enabling signal of each data storing element in the chain to allow shifting samples through an end portion of the clocked delay chain on a selected first set of clock cycles determining a first shifting rate and shifting data samples in an initial portion of the delay chain on a selected second set of clock cycles determining a second shifting rate, wherein the initial portion is complementary to the end portion and wherein the first shifting rate is higher than the second shifting rate;
reducing the length of the clocked delay chain by moving the output of the delay chain to the last register of the initial portion, after a number of clock cycles; and
repeating the steps of shifting data samples through an end portion of the reduced delay chain and through the initial portion and reducing the length of the clocked delay chain.