Technique for filter-enhanced clock synchronization
View Patent ↗A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element. And the method further comprises subjecting the first output signal to a second EWMA filter to generate a second output signal, where the second EWMA filter comprises a second gain element and the second EWMA filter is coupled with a feedback loop having a delay element and a summing junction.
1. A method for filter-enhanced clock synchronization, the method comprising:
subjecting a clock error signal to a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element; and
subjecting the first output signal to a second EWMA filter to generate a second output signal, where the second EWMA filter comprises a second gain element;
wherein the first EWMA filter is coupled with a first feedback loop having a first delay element and a first summing junction;
wherein the second EWMA filter is coupled to a second feedback loop having a second delay element and a second summing junction.
2. The method according to claim 1 , where at least one of the first gain element and the second gain element is a tunable gain element.
3. The method according to claim 2 , further comprising tuning at least one of the first gain element and the second gain element to achieve a desired response time and performance for the second output signal.
4. The method according to claim 1 , wherein the second feedback loop comprises a third gain element.
5. The method according to claim 4 , where the third gain element is a tunable gain element.
6. The method according to claim 5 , further comprising tuning the third gain element, in addition to the first gain element and the second gain element, to achieve a desired response time and performance for the second output signal.
7. The method according to claim 1 , where the first feedback loop comprises a third gain element.
8. The method according to claim 7 , where the third gain element is a tunable gain element.
9. At least one computer readable medium for storing instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 1 .
10. An apparatus for filter-enhanced clock synchronization, the apparatus comprising:
a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element; and
a second EWMA filter to receive the first output signal and generate a second output signal, where the second EWMA filter comprises a second gain element;
wherein the first EWMA filter is coupled with a first feedback loop having a first delay element and a first summing junction;
wherein the second EWMA filter is coupled to a second feedback loop having a second delay element and a second summing junction.
11. The apparatus according to claim 10 , where at least one of the first gain element and the second gain element is a tunable gain element.
12. The apparatus according to claim 11 , where at least one of the first gain element and the second gain element is tuned to achieve a desired response time and performance for the second output signal.
13. The apparatus according to claim 10 , wherein the second feedback loop comprises a third gain element.
14. The apparatus according to claim 13 , where the third gain element is a tunable gain element.
15. The apparatus according to claim 14 , where the third gain element is tuned, in addition to the first gain element and the second gain element, to achieve a desired response time and performance for the second output signal.
16. The apparatus according to claim 10 , where the first feedback loop comprises a third gain element.
17. The apparatus according to claim 16 , where the third gain element is a tunable gain element.